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| REJ09B0427-0100 16 H8S/2607 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series H8S/2607 H8S/2606 H8S/2605 HD64F2607 HD6432607 HD6432606 HD6432605 Rev.1.00 Revision Date: Jan. 29, 2008 Rev. 1.00 Jan. 29, 2008 Page ii of xl Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev. 1.00 Jan. 29, 2008 Page iii of xl General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 1.00 Jan. 29, 2008 Page iv of xl Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules * CPU and System-Control Modules * On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 1.00 Jan. 29, 2008 Page v of xl Preface The H8S/2607 Group single-chip microcomputer is made up of the high-speed H8S/2600 CPU as its core, and the peripheral functions required configuring a system. The H8S/2600 CPU has an instruction set that is compatible with the H8/300 and H8/300H CPUs. Target Users: This manual was written for users who will be using the H8S/2607 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the H8S/2607 Group to the target users. Refer to the H8S/2600 Series, H8S/2000 Series Software Manual for a detailed description of the instruction set. Notes on reading this manual: * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions, and electrical characteristics. * In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Software Manual. * In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 22, List of Registers. Examples: Register name: The following notation is used for cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ Rev. 1.00 Jan. 29, 2008 Page vi of xl H8S/2607 Group manuals: Document Title H8S/2607 Group Hardware Manual H8S/2600 Series, H8S/2000 Series Software Manual Document No. This manual REJ09B0139 User's manuals for development tools: Document Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual Microcomputer Development Environment System H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series High-performance Embedded Workshop 3 Tutorial H8S, H8/300 Series High-performance Embedded Workshop 3 User's Manual Document No. REJ10B0058 ADE-702-037 REJ10B0024 REJ10B0026 All trademarks and registered trademarks are the property of their respective owners. Rev. 1.00 Jan. 29, 2008 Page vii of xl Rev. 1.00 Jan. 29, 2008 Page viii of xl Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 Features.................................................................................................................................. 1 Block Diagram....................................................................................................................... 3 Pin Assignments .................................................................................................................... 4 1.3.1 Pin Assignments ....................................................................................................... 4 1.3.2 Pin Functions in Each Operating Mode .................................................................... 5 1.3.3 Pin Functions .......................................................................................................... 10 Section 2 CPU......................................................................................................15 2.1 Features................................................................................................................................ 15 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................... 16 2.1.2 Differences from H8/300 CPU ............................................................................... 17 2.1.3 Differences from H8/300H CPU ............................................................................ 17 CPU Operating Modes......................................................................................................... 18 2.2.1 Normal Mode.......................................................................................................... 18 2.2.2 Advanced Mode...................................................................................................... 20 Address Space...................................................................................................................... 22 Registers .............................................................................................................................. 23 2.4.1 General Registers.................................................................................................... 24 2.4.2 Program Counter (PC) ............................................................................................ 25 2.4.3 Extended Control Register (EXR) .......................................................................... 25 2.4.4 Condition-Code Register (CCR)............................................................................. 26 2.4.5 Multiply-Accumulate Register (MAC)................................................................... 27 2.4.6 Initial Values of CPU Registers.............................................................................. 27 Data Formats........................................................................................................................ 28 2.5.1 General Register Data Formats............................................................................... 28 2.5.2 Memory Data Formats ............................................................................................ 30 Instruction Set ...................................................................................................................... 31 2.6.1 Table of Instructions Classified by Function .......................................................... 32 2.6.2 Basic Instruction Formats ....................................................................................... 42 Addressing Modes and Effective Address Calculation........................................................ 43 2.7.1 Register DirectRn ............................................................................................... 43 2.7.2 Register Indirect@ERn....................................................................................... 43 2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn)................. 44 2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn..... 44 2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32....................................... 44 2.2 2.3 2.4 2.5 2.6 2.7 Rev. 1.00 Jan. 29, 2008 Page ix of xl 2.8 2.9 2.7.6 Immediate#xx:8, #xx:16, or #xx:32.................................................................... 45 2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC) ...................................... 45 2.7.8 Memory Indirect@@aa:8 ................................................................................... 45 2.7.9 Effective Address Calculation ................................................................................ 46 Processing States.................................................................................................................. 49 Usage Note........................................................................................................................... 51 2.9.1 Notes on Using the Bit Operation Instruction......................................................... 51 Section 3 MCU Operating Modes .......................................................................53 3.1 3.2 Operating Mode Selection ................................................................................................... 53 Register Descriptions ........................................................................................................... 54 3.2.1 Mode Control Register (MDCR) ............................................................................ 54 3.2.2 System Control Register (SYSCR)......................................................................... 55 Operating Mode Descriptions .............................................................................................. 56 3.3.1 Mode 4.................................................................................................................... 56 3.3.2 Mode 5.................................................................................................................... 56 3.3.3 Mode 6.................................................................................................................... 56 3.3.4 Mode 7.................................................................................................................... 56 Pin Functions in Each Operating Mode ............................................................................... 57 Address Map ........................................................................................................................ 58 3.3 3.4 3.5 Section 4 Exception Handling .............................................................................61 4.1 4.2 4.3 Exception Handling Types and Priority............................................................................... 61 Exception Sources and Exception Vector Table .................................................................. 62 Reset .................................................................................................................................... 63 4.3.1 Reset Exception Handling ...................................................................................... 63 4.3.2 Interrupts after Reset............................................................................................... 66 4.3.3 State of On-Chip Peripheral Modules after Reset Release ..................................... 66 Traces................................................................................................................................... 66 Interrupts.............................................................................................................................. 67 Trap Instruction.................................................................................................................... 68 Stack Status after Exception Handling................................................................................. 69 Usage Note........................................................................................................................... 70 4.4 4.5 4.6 4.7 4.8 Section 5 Interrupt Controller.............................................................................. 71 5.1 5.2 5.3 Features................................................................................................................................ 71 Input/Output Pins................................................................................................................. 73 Register Descriptions ........................................................................................................... 74 5.3.1 Interrupt Priority Registers A to H, J, K, L, and M (IPRA to IPRH, IPRJ, IPRK, IPRL, and IPRM)..................................................... 75 Rev. 1.00 Jan. 29, 2008 Page x of xl 5.4 5.5 5.6 5.7 5.3.2 IRQ Enable Register (IER) ..................................................................................... 76 5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)........................................ 77 5.3.4 IRQ Status Register (ISR)....................................................................................... 79 Interrupt Sources.................................................................................................................. 80 5.4.1 External Interrupts .................................................................................................. 80 5.4.2 Internal Interrupts ................................................................................................... 81 Interrupt Exception Handling Vector Table......................................................................... 81 Interrupt Control Modes and Interrupt Operation ................................................................ 85 5.6.1 Interrupt Control Mode 0........................................................................................ 85 5.6.2 Interrupt Control Mode 2........................................................................................ 87 5.6.3 Interrupt Exception Handling Sequence ................................................................. 89 5.6.4 Interrupt Response Times ....................................................................................... 91 5.6.5 DTC Activation by Interrupt................................................................................... 92 Usage Notes ......................................................................................................................... 93 5.7.1 Conflict between Interrupt Generation and Disabling ............................................ 93 5.7.2 Instructions that Disable Interrupts......................................................................... 94 5.7.3 When Interrupts Are Disabled ................................................................................ 94 5.7.4 Interrupts during Execution of EEPMOV Instruction ............................................ 94 Section 6 PC Break Controller (PBC) .................................................................95 6.1 6.2 Features................................................................................................................................ 95 Register Descriptions ........................................................................................................... 96 6.2.1 Break Address Register A (BARA) ........................................................................ 96 6.2.2 Break Address Register B (BARB) ........................................................................ 97 6.2.3 Break Control Register A (BCRA) ......................................................................... 97 6.2.4 Break Control Register B (BCRB) ......................................................................... 98 Operation ............................................................................................................................. 98 6.3.1 PC Break Interrupt Due to Instruction Fetch .......................................................... 98 6.3.2 PC Break Interrupt Due to Data Access.................................................................. 99 6.3.3 PC Break Operation at Consecutive Data Transfer................................................. 99 6.3.4 Operation in Transitions to Power-Down Modes ................................................... 99 6.3.5 When Instruction Execution Is Delayed by One State.......................................... 101 Usage Notes ....................................................................................................................... 102 6.4.1 Module Stop Mode Setting ................................................................................... 102 6.4.2 PC Break Interrupts .............................................................................................. 102 6.4.3 CMFA and CMFB ................................................................................................ 102 6.4.4 PC Break Interrupt when DTC Is Bus Master ...................................................... 102 6.4.5 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA, RTE, or RTS Instruction ........................... 102 6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction ........................................ 102 Rev. 1.00 Jan. 29, 2008 Page xi of xl 6.3 6.4 6.4.7 6.4.8 PC Break Set for Instruction Fetch at Address Following Bcc Instruction........... 103 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc Instruction ................................................................................................. 103 Section 7 Bus Controller (BSC) ........................................................................105 7.1 7.2 7.3 Features.............................................................................................................................. 105 Input/Output Pins............................................................................................................... 107 Register Descriptions ......................................................................................................... 107 7.3.1 Bus Width Control Register (ABWCR)................................................................ 108 7.3.2 Access State Control Register (ASTCR) .............................................................. 108 7.3.3 Wait Control Registers H and L (WCRH and WCRL)......................................... 109 7.3.4 Bus Control Register H (BCRH) .......................................................................... 111 7.3.5 Bus Control Register L (BCRL) ........................................................................... 112 7.3.6 Pin Function Control Register (PFCR) ................................................................. 113 7.4 Bus Control........................................................................................................................ 114 7.4.1 Area Division........................................................................................................ 114 7.4.2 Bus Specifications ................................................................................................ 115 7.4.3 Memory Interfaces................................................................................................ 116 7.5 Basic Bus Interface ............................................................................................................ 117 7.5.1 Data Size and Data Alignment.............................................................................. 117 7.5.2 Valid Strobes ........................................................................................................ 119 7.5.3 Basic Timing......................................................................................................... 120 7.5.4 Wait Control ......................................................................................................... 127 7.6 Burst ROM Interface.......................................................................................................... 129 7.6.1 Basic Timing......................................................................................................... 129 7.6.2 Wait Control ......................................................................................................... 131 7.6.3 Write Access......................................................................................................... 131 7.7 Idle Cycle........................................................................................................................... 132 7.7.1 Operation .............................................................................................................. 132 7.7.2 Pin States in Idle Cycle......................................................................................... 134 7.8 Write Data Buffer Function ............................................................................................... 135 7.9 Bus Arbitration .................................................................................................................. 136 7.9.1 Operation .............................................................................................................. 136 7.9.2 Bus Transfer Timing............................................................................................. 136 7.10 Bus Controller Operation in Reset ..................................................................................... 137 Section 8 Data Transfer Controller (DTC)........................................................ 139 8.1 8.2 Features.............................................................................................................................. 139 Register Descriptions ......................................................................................................... 141 8.2.1 DTC Mode Register A (MRA) ............................................................................. 142 Rev. 1.00 Jan. 29, 2008 Page xii of xl 8.3 8.4 8.5 8.6 8.7 8.8 8.2.2 DTC Mode Register B (MRB).............................................................................. 143 8.2.3 DTC Source Address Register (SAR)................................................................... 144 8.2.4 DTC Destination Address Register (DAR)........................................................... 144 8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 144 8.2.6 DTC Transfer Count Register B (CRB)................................................................ 144 8.2.7 DTC Enable Registers A to G, and I (DTCERA to DTCERG) ............................ 145 8.2.8 DTC Vector Registers A to G (DTVECRA to DTVECRG)................................. 146 Activation Sources............................................................................................................. 147 Location of Register Information and DTC Vector Table ................................................. 148 Operation ........................................................................................................................... 151 8.5.1 Normal Mode........................................................................................................ 152 8.5.2 Repeat Mode......................................................................................................... 153 8.5.3 Block Transfer Mode ............................................................................................ 154 8.5.4 Chain Transfer ...................................................................................................... 156 8.5.5 Interrupts............................................................................................................... 157 8.5.6 Operation Timing.................................................................................................. 157 8.5.7 Number of DTC Execution States ........................................................................ 159 Procedures for Using DTC................................................................................................. 160 8.6.1 Activation by Interrupt.......................................................................................... 160 8.6.2 Activation by Software ......................................................................................... 160 Examples of Use of the DTC ............................................................................................. 161 8.7.1 Normal Mode........................................................................................................ 161 8.7.2 Chain Transfer ...................................................................................................... 162 8.7.3 Software Activation .............................................................................................. 163 Usage Notes ....................................................................................................................... 164 8.8.1 Module Stop Mode Setting ................................................................................... 164 8.8.2 On-Chip RAM ...................................................................................................... 164 8.8.3 DTCE Bit Setting.................................................................................................. 164 Section 9 I/O Ports.............................................................................................165 9.1 Port 1.................................................................................................................................. 170 9.1.1 Port 1 Data Direction Register (P1DDR).............................................................. 170 9.1.2 Port 1 Data Register (P1DR)................................................................................. 171 9.1.3 Port 1 Register (PORT1)....................................................................................... 171 9.1.4 Pin Functions ........................................................................................................ 172 Port 3.................................................................................................................................. 184 9.2.1 Port 3 Data Direction Register (P3DDR).............................................................. 184 9.2.2 Port 3 Data Register (P3DR)................................................................................. 185 9.2.3 Port 3 Register (PORT3)....................................................................................... 185 9.2.4 Port 3 Open-Drain Control Register (P3ODR) ..................................................... 186 Rev. 1.00 Jan. 29, 2008 Page xiii of xl 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.2.5 Pin Functions ........................................................................................................ 186 Port 4.................................................................................................................................. 189 9.3.1 Port 4 Register (PORT4)....................................................................................... 189 9.3.2 Pin Functions ........................................................................................................ 189 Port 9.................................................................................................................................. 190 9.4.1 Port 9 Register (PORT9)....................................................................................... 190 9.4.2 Pin Functions ........................................................................................................ 190 Port A................................................................................................................................. 191 9.5.1 Port A Data Direction Register (PADDR)............................................................ 191 9.5.2 Port A Data Register (PADR)............................................................................... 192 9.5.3 Port A Register (PORTA)..................................................................................... 192 9.5.4 Port A Pull-Up MOS Control Register (PAPCR) ................................................. 193 9.5.5 Port A Open-Drain Control Register (PAODR) ................................................... 193 9.5.6 Pin Functions ........................................................................................................ 194 Port B ................................................................................................................................. 197 9.6.1 Port B Data Direction Register (PBDDR) ............................................................ 197 9.6.2 Port B Data Register (PBDR) ............................................................................... 198 9.6.3 Port B Register (PORTB) ..................................................................................... 198 9.6.4 Port B Pull-Up MOS Control Register (PBPCR) ................................................. 199 9.6.5 Port B Open-Drain Control Register (PBODR).................................................... 199 9.6.6 Pin Functions ........................................................................................................ 200 Port C ................................................................................................................................. 208 9.7.1 Port C Data Direction Register (PCDDR) ............................................................ 208 9.7.2 Port C Data Register (PCDR) ............................................................................... 209 9.7.3 Port C Register (PORTC) ..................................................................................... 209 9.7.4 Port C Pull-Up MOS Control Register (PCPCR) ................................................. 210 9.7.5 Port C Open-Drain Control Register (PCODR).................................................... 210 9.7.6 Pin Functions ........................................................................................................ 211 Port D................................................................................................................................. 212 9.8.1 Port D Data Direction Register (PDDDR)............................................................ 212 9.8.2 Port D Data Register (PDDR)............................................................................... 213 9.8.3 Port D Register (PORTD)..................................................................................... 213 9.8.4 Port D Pull-Up MOS Control Register (PDPCR) ................................................. 214 9.8.5 Pin Functions ........................................................................................................ 214 Port E ................................................................................................................................. 215 9.9.1 Port E Data Direction Register (PEDDR)............................................................. 215 9.9.2 Port E Data Register (PEDR)................................................................................ 216 9.9.3 Port E Register (PORTE)...................................................................................... 216 9.9.4 Port E Pull-Up MOS Control Register (PEPCR).................................................. 217 9.9.5 Pin Functions ........................................................................................................ 217 Rev. 1.00 Jan. 29, 2008 Page xiv of xl 9.10 Port F ................................................................................................................................. 218 9.10.1 Port F Data Direction Register (PFDDR) ............................................................. 218 9.10.2 Port F Data Register (PFDR) ................................................................................ 219 9.10.3 Port F Register (PORTF) ...................................................................................... 219 9.10.4 Pin Functions ........................................................................................................ 220 9.11 Port H................................................................................................................................. 222 9.11.1 Port H Data Direction Register (PHDDR)............................................................ 222 9.11.2 Port H Data Register (PHDR)............................................................................... 223 9.11.3 Port H Register (PORTH)..................................................................................... 223 9.11.4 Pin Functions ........................................................................................................ 224 9.12 Port J .................................................................................................................................. 225 9.12.1 Port J Data Direction Register (PJDDR)............................................................... 225 9.12.2 Port J Data Register (PJDR) ................................................................................. 226 9.12.3 Port J Register (PORTJ) ....................................................................................... 226 9.12.4 Pin Functions ........................................................................................................ 227 Section 10 16-Bit Timer Pulse Unit (TPU) .......................................................229 10.1 Features.............................................................................................................................. 229 10.2 Input/Output Pins............................................................................................................... 234 10.3 Register Descriptions ......................................................................................................... 235 10.3.1 Timer Control Register (TCR).............................................................................. 237 10.3.2 Timer Mode Register (TMDR)............................................................................. 242 10.3.3 Timer I/O Control Register (TIOR)...................................................................... 244 10.3.4 Timer Interrupt Enable Register (TIER)............................................................... 261 10.3.5 Timer Status Register (TSR)................................................................................. 263 10.3.6 Timer Counter (TCNT)......................................................................................... 266 10.3.7 Timer General Register (TGR) ............................................................................. 266 10.3.8 Timer Start Register (TSTR) ................................................................................ 266 10.3.9 Timer Synchro Register (TSYR) .......................................................................... 267 10.4 Operation ........................................................................................................................... 268 10.4.1 Basic Functions..................................................................................................... 268 10.4.2 Synchronous Operation......................................................................................... 274 10.4.3 Buffer Operation................................................................................................... 276 10.4.4 Cascaded Operation .............................................................................................. 280 10.4.5 PWM Modes......................................................................................................... 282 10.4.6 Phase Counting Mode........................................................................................... 287 10.5 Interrupt Sources................................................................................................................ 293 10.6 DTC Activation.................................................................................................................. 295 10.7 A/D Converter Activation.................................................................................................. 295 10.8 Operation Timing............................................................................................................... 296 Rev. 1.00 Jan. 29, 2008 Page xv of xl 10.8.1 Input/Output Timing ............................................................................................. 296 10.8.2 Interrupt Signal Timing ........................................................................................ 300 10.9 Usage Notes ....................................................................................................................... 304 10.9.1 Module Stop Mode Setting ................................................................................... 304 10.9.2 Input Clock Restrictions ....................................................................................... 304 10.9.3 Caution on Period Setting ..................................................................................... 305 10.9.4 Conflict between TCNT Write and Clear Operations .......................................... 305 10.9.5 Conflict between TCNT Write and Increment Operations ................................... 306 10.9.6 Conflict between TGR Write and Compare Match............................................... 307 10.9.7 Conflict between Buffer Register Write and Compare Match .............................. 308 10.9.8 Conflict between TGR Read and Input Capture ................................................... 309 10.9.9 Conflict between TGR Write and Input Capture .................................................. 310 10.9.10 Conflict between Buffer Register Write and Input Capture.................................. 311 10.9.11 Conflict between Overflow/Underflow and Counter Clearing ............................. 312 10.9.12 Conflict between TCNT Write and Overflow/Underflow .................................... 313 10.9.13 Multiplexing of I/O Pins ....................................................................................... 313 10.9.14 Interrupts in Module Stop Mode........................................................................... 313 Section 11 Programmable Pulse Generator (PPG) ............................................315 11.1 Features.............................................................................................................................. 315 11.2 Input/Output Pins............................................................................................................... 317 11.3 Register Descriptions ......................................................................................................... 317 11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ......................................... 318 11.3.2 Output Data Registers H, L (PODRH, PODRL)................................................... 319 11.3.3 Next Data Registers H, L (NDRH, NDRL) .......................................................... 320 11.3.4 PPG Output Control Register (PCR) .................................................................... 323 11.3.5 PPG Output Mode Register (PMR) ...................................................................... 324 11.4 Operation ........................................................................................................................... 325 11.4.1 Overview .............................................................................................................. 325 11.4.2 Output Timing ...................................................................................................... 326 11.4.3 Sample Setup Procedure for Normal Pulse Output............................................... 327 11.4.4 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)........... 328 11.4.5 Non-Overlapping Pulse Output............................................................................. 329 11.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output............................... 331 11.4.7 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) .................. 332 11.4.8 Inverted Pulse Output ........................................................................................... 334 11.4.9 Pulse Output Triggered by Input Capture ............................................................. 335 11.5 Usage Notes ....................................................................................................................... 336 11.5.1 Module Stop Mode Setting ................................................................................... 336 Rev. 1.00 Jan. 29, 2008 Page xvi of xl 11.5.2 Operation of Pulse Output Pins............................................................................. 336 Section 12 Watchdog Timer (WDT) .................................................................337 12.1 Features.............................................................................................................................. 337 12.2 Register Descriptions ......................................................................................................... 339 12.2.1 Timer Counter (TCNT)......................................................................................... 339 12.2.2 Timer Control/Status Register (TCSR)................................................................. 339 12.2.3 Reset Control/Status Register (RSTCSR)............................................................. 343 12.3 Operation ........................................................................................................................... 344 12.3.1 Watchdog Timer Mode......................................................................................... 344 12.3.2 Interval Timer Mode............................................................................................. 346 12.4 Interrupt Sources................................................................................................................ 346 12.5 Usage Notes ....................................................................................................................... 347 12.5.1 Notes on Register Access ..................................................................................... 347 12.5.2 Contention between Timer Counter (TCNT) Write and Increment ...................... 348 12.5.3 Changing Value of CKS2 to CKS0 ...................................................................... 348 12.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode................. 348 12.5.5 Internal Reset in Watchdog Timer Mode.............................................................. 349 12.5.6 OVF Flag Clearing in Interval Timer Mode ......................................................... 349 Section 13 Serial Communication Interface (SCI) ............................................351 13.1 Features.............................................................................................................................. 351 13.2 Input/Output Pins............................................................................................................... 353 13.3 Register Descriptions ......................................................................................................... 354 13.3.1 Receive Shift Register (RSR) ............................................................................... 354 13.3.2 Receive Data Register (RDR)............................................................................... 354 13.3.3 Transmit Data Register (TDR).............................................................................. 355 13.3.4 Transmit Shift Register (TSR) .............................................................................. 355 13.3.5 Serial Mode Register (SMR) ................................................................................ 355 13.3.6 Serial Control Register (SCR) .............................................................................. 358 13.3.7 Serial Status Register (SSR) ................................................................................. 361 13.3.8 Smart Card Mode Register (SCMR)..................................................................... 365 13.3.9 Bit Rate Register (BRR) ....................................................................................... 366 13.4 Operation in Asynchronous Mode ..................................................................................... 373 13.4.1 Data Transfer Format............................................................................................ 373 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode......................................................................................... 375 13.4.3 Clock..................................................................................................................... 376 13.4.4 SCI Initialization (Asynchronous Mode).............................................................. 377 13.4.5 Data Transmission (Asynchronous Mode) ........................................................... 378 Rev. 1.00 Jan. 29, 2008 Page xvii of xl 13.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 380 13.5 Multiprocessor Communication Function.......................................................................... 384 13.5.1 Multiprocessor Serial Data Transmission ............................................................. 386 13.5.2 Multiprocessor Serial Data Reception .................................................................. 388 13.6 Operation in Clocked Synchronous Mode ......................................................................... 391 13.6.1 Clock..................................................................................................................... 391 13.6.2 SCI Initialization (Clocked Synchronous Mode).................................................. 392 13.6.3 Serial Data Transmission (Clocked Synchronous Mode) ..................................... 393 13.6.4 Serial Data Reception (Clocked Synchronous Mode) .......................................... 396 13.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) .............................................................................. 398 13.7 Operation in Smart Card Interface ..................................................................................... 400 13.7.1 Pin Connection Example ...................................................................................... 400 13.7.2 Data Format (Except for Block Transfer Mode)................................................... 401 13.7.3 Block Transfer Mode ............................................................................................ 402 13.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode............................................................................... 403 13.7.5 Initialization.......................................................................................................... 404 13.7.6 Data Transmission (Except for Block Transfer Mode)......................................... 405 13.7.7 Serial Data Reception (Except for Block Transfer Mode).................................... 408 13.7.8 Clock Output Control............................................................................................ 410 13.8 Interrupt Sources................................................................................................................ 412 13.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 412 13.8.2 Interrupts in Smart Card Interface Mode .............................................................. 414 13.9 Usage Notes ....................................................................................................................... 416 13.9.1 Module Stop Mode Setting ................................................................................... 416 13.9.2 Break Detection and Processing ........................................................................... 416 13.9.3 Mark State and Break Detection ........................................................................... 416 13.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) ..................................................................... 416 13.9.5 Restrictions on Using DTC................................................................................... 417 13.9.6 SCI Operations during Mode Transitions ............................................................. 417 13.9.7 Notes when Switching from SCK Pin to Port Pin................................................. 421 Section 14 I2C Bus Interface..............................................................................423 14.1 Features.............................................................................................................................. 423 14.2 Input/Output Pins............................................................................................................... 426 14.3 Register Configuration....................................................................................................... 427 14.3.1 I2C Bus Data Register (ICDR) .............................................................................. 427 14.3.2 Slave Address Register (SAR).............................................................................. 429 Rev. 1.00 Jan. 29, 2008 Page xviii of xl 14.3.3 Second Slave Address Register (SARX) .............................................................. 430 14.3.4 I2C Bus Mode Register (ICMR)............................................................................ 432 14.3.5 I2C Bus Control Register (ICCR).......................................................................... 435 14.3.6 I2C Bus Status Register (ICSR)............................................................................. 441 14.3.7 Serial Control Register X (SCRX)........................................................................ 446 14.3.8 DDC Switch Register (DDCSWR)....................................................................... 447 14.4 Operation ........................................................................................................................... 448 14.4.1 I2C Bus Data Format ............................................................................................. 448 14.4.2 Initial Setting ........................................................................................................ 450 14.4.3 Master Transmit Operation................................................................................... 451 14.4.4 Master Receive Operation .................................................................................... 455 14.4.5 Slave Receive Operation....................................................................................... 460 14.4.6 Slave Transmit Operation ..................................................................................... 464 14.4.7 IRIC Setting Timing and SCL Control ................................................................. 468 14.4.8 Operation Using the DTC ..................................................................................... 469 14.4.9 Noise Canceler...................................................................................................... 470 14.4.10 Initialization of Internal State ............................................................................... 470 14.5 Usage Notes ....................................................................................................................... 472 Section 15 A/D Converter..................................................................................485 15.1 Features.............................................................................................................................. 485 15.2 Input/Output Pins............................................................................................................... 487 15.3 Register Description .......................................................................................................... 488 15.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 488 15.3.2 A/D Control/Status Register (ADCSR) ................................................................ 489 15.3.3 A/D Control Register (ADCR) ............................................................................. 491 15.4 Operation ........................................................................................................................... 492 15.4.1 Single Mode.......................................................................................................... 492 15.4.2 Scan Mode ............................................................................................................ 492 15.4.3 Input Sampling and A/D Conversion Time .......................................................... 493 15.4.4 External Trigger Input Timing.............................................................................. 495 15.5 Interrupts............................................................................................................................ 495 15.6 A/D Conversion Precision Definitions .............................................................................. 496 15.7 Usage Notes ....................................................................................................................... 498 15.7.1 Module Stop Mode Setting ................................................................................... 498 15.7.2 Permissible Signal Source Impedance .................................................................. 498 15.7.3 Influences on Absolute Precision.......................................................................... 498 15.7.4 Range of Analog Power Supply and Other Pin Settings....................................... 499 15.7.5 Notes on Board Design ......................................................................................... 499 15.7.6 Notes on Noise Countermeasures ......................................................................... 500 Rev. 1.00 Jan. 29, 2008 Page xix of xl Section 16 D/A Converter ................................................................................. 503 16.1 Features.............................................................................................................................. 503 16.2 Input/Output Pins............................................................................................................... 504 16.3 Register Descriptions ......................................................................................................... 504 16.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) .................................................. 504 16.3.2 D/A Control Register (DACR) ............................................................................. 505 16.4 Operation ........................................................................................................................... 506 16.5 Usage Note......................................................................................................................... 508 16.5.1 Module Stop Mode Setting ................................................................................... 508 Section 17 Motor Control PWM Timer (PWM) ...............................................509 17.1 Features.............................................................................................................................. 509 17.2 Input/Output Pins............................................................................................................... 512 17.3 Register Descriptions ......................................................................................................... 513 17.3.1 PWM Control Register (PWCR) .......................................................................... 514 17.3.2 PWM Output Control Register (PWOCR)............................................................ 515 17.3.3 PWM Polarity Register (PWPR) .......................................................................... 516 17.3.4 PWM Counter (PWCNT) ..................................................................................... 516 17.3.5 PWM Cycle Register (PWCYR) .......................................................................... 517 17.3.6 PWM Duty Registers (PWDTR) .......................................................................... 518 17.3.7 PWM Buffer Register (PWBFR) .......................................................................... 523 17.4 Bus Master Interface .......................................................................................................... 525 17.4.1 16-Bit Data Registers............................................................................................ 525 17.4.2 8-Bit Data Registers.............................................................................................. 525 17.5 Operation ........................................................................................................................... 526 17.5.1 PWM_1 Operation................................................................................................ 526 17.5.2 PWM_2 Operation................................................................................................ 527 17.6 Usage Note......................................................................................................................... 529 17.6.1 Conflict between Buffer Register Write and Compare Match .............................. 529 Section 18 RAM ................................................................................................ 531 Section 19 ROM ................................................................................................ 533 19.1 19.2 19.3 19.4 19.5 Features.............................................................................................................................. 533 Mode Transitions ............................................................................................................... 534 Block Configuration .......................................................................................................... 538 Input/Output Pins............................................................................................................... 540 Register Descriptions ......................................................................................................... 540 19.5.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 541 19.5.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 542 Rev. 1.00 Jan. 29, 2008 Page xx of xl 19.6 19.7 19.8 19.9 19.10 19.11 19.12 19.13 19.5.3 Erase Block Register 1 (EBR1) ............................................................................ 543 19.5.4 Erase Block Register 2 (EBR2) ............................................................................ 544 19.5.5 RAM Emulation Register (RAMER).................................................................... 545 19.5.6 Flash Memory Power Control Register (FLPWCR)............................................. 546 On-Board Programming Modes......................................................................................... 547 19.6.1 Boot Mode ............................................................................................................ 547 19.6.2 Programming/Erasing in User Program Mode...................................................... 550 Flash Memory Emulation in RAM .................................................................................... 551 Flash Memory Programming/Erasing ................................................................................ 554 19.8.1 Program/Program-Verify ...................................................................................... 554 19.8.2 Erase/Erase-Verify................................................................................................ 556 19.8.3 Interrupt Handling when Programming/Erasing Flash Memory........................... 556 Program/Erase Protection .................................................................................................. 558 19.9.1 Hardware Protection ............................................................................................. 558 19.9.2 Software Protection............................................................................................... 558 19.9.3 Error Protection .................................................................................................... 558 Interrupt Handling when Programming/Erasing Flash Memory........................................ 559 Programmer Mode ............................................................................................................. 560 Power-Down States for Flash Memory.............................................................................. 560 Usage Notes ....................................................................................................................... 561 Section 20 Clock Pulse Generator .....................................................................565 20.1 Register Descriptions ......................................................................................................... 566 20.1.1 System Clock Control Register (SCKCR) ............................................................ 566 20.2 Oscillator............................................................................................................................ 568 20.2.1 Connecting a Crystal Resonator............................................................................ 568 20.2.2 External Clock Input............................................................................................. 569 20.3 PLL Circuit ........................................................................................................................ 571 20.4 Medium-Speed Clock Divider ........................................................................................... 571 20.5 Bus Master Clock Selection Circuit................................................................................... 571 20.6 Subclock Oscillator............................................................................................................ 572 20.6.1 Connecting 32.768-kHz Crystal Resonator .......................................................... 572 20.6.2 Handling Pins when Subclock is not Used ........................................................... 573 20.7 Subclock Waveform Generation Circuit............................................................................ 573 20.8 Usage Notes ....................................................................................................................... 573 20.8.1 Note on Crystal Resonator.................................................................................... 573 20.8.2 Note on Board Design........................................................................................... 574 Section 21 Power-Down Modes ........................................................................575 21.1 Register Descriptions ......................................................................................................... 579 Rev. 1.00 Jan. 29, 2008 Page xxi of xl 21.2 21.3 21.4 21.5 21.6 21.7 21.8 21.9 21.10 21.11 21.12 21.1.1 Standby Control Register (SBYCR) ..................................................................... 579 21.1.2 Low-Power Control Register (LPWRCR) ............................................................ 582 21.1.3 Module Stop Control Registers A to D (MSTPCRA to MSTPCRD) ................... 583 Medium-Speed Mode......................................................................................................... 585 Sleep Mode ........................................................................................................................ 586 Software Standby Mode..................................................................................................... 587 Hardware Standby Mode ................................................................................................... 589 Watch Mode....................................................................................................................... 590 Subsleep Mode................................................................................................................... 591 Subactive Mode ................................................................................................................. 591 Module Stop Mode ............................................................................................................ 592 Direct Transitions .............................................................................................................. 593 21.10.1 Overview of Direct Transitions ............................................................................ 593 Clock Output Control...................................................................................................... 594 Usage Notes ....................................................................................................................... 595 21.12.1 I/O Port Status....................................................................................................... 595 21.12.2 Current Consumption during Oscillation Stabilization Wait Period..................... 595 21.12.3 DTC Module Stop Setting .................................................................................... 595 21.12.4 On-Chip Peripheral Module Interrupts ................................................................. 595 21.12.5 Writing to MSTPCR ............................................................................................. 595 21.12.6 Transition to Subactive Mode............................................................................... 596 Section 22 List of Registers............................................................................... 597 22.1 Register Addresses (Address Order).................................................................................. 598 22.2 Register Bits....................................................................................................................... 607 22.3 Register States in Each Operating Mode ........................................................................... 616 Section 23 Electrical Characteristics .................................................................625 23.1 Absolute Maximum Ratings .............................................................................................. 625 23.2 DC Characteristics ............................................................................................................. 626 23.3 AC Characteristics ............................................................................................................. 632 23.3.1 Clock Timing ........................................................................................................ 633 23.3.2 Control Signal Timing .......................................................................................... 635 23.3.3 Bus Timing ........................................................................................................... 637 23.3.4 Timing of On-Chip Supporting Modules.............................................................. 643 23.4 I2C Bus Interface Timing ................................................................................................... 647 23.5 A/D Conversion Characteristics......................................................................................... 649 23.6 D/A Conversion Characteristics......................................................................................... 650 23.7 Flash Memory Characteristics ........................................................................................... 651 23.8 Usage Note......................................................................................................................... 653 Rev. 1.00 Jan. 29, 2008 Page xxii of xl Appendix A. B. C. .........................................................................................................655 I/O Port States in Each Operating State ............................................................................. 655 Product Code Lineup ......................................................................................................... 658 Package Dimensions .......................................................................................................... 659 Index .........................................................................................................661 Rev. 1.00 Jan. 29, 2008 Page xxiii of xl Rev. 1.00 Jan. 29, 2008 Page xxiv of xl Figures Section 1 Overview Figure 1.1 Block Diagram .............................................................................................................. 3 Figure 1.2 Pin Assignments............................................................................................................ 4 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 19 Figure 2.2 Stack Structure in Normal Mode................................................................................. 19 Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 20 Figure 2.4 Stack Structure in Advanced Mode............................................................................. 21 Figure 2.5 Memory Map............................................................................................................... 22 Figure 2.6 CPU Registers ............................................................................................................. 23 Figure 2.7 Usage of General Registers ......................................................................................... 24 Figure 2.8 Stack............................................................................................................................ 25 Figure 2.9 General Register Data Formats (1).............................................................................. 28 Figure 2.9 General Register Data Formats (2).............................................................................. 29 Figure 2.10 Memory Data Formats............................................................................................... 30 Figure 2.11 Instruction Formats (Examples) ................................................................................ 42 Figure 2.12 Branch Address Specification in Memory Indirect Mode ......................................... 46 Figure 2.13 State Transitions........................................................................................................ 50 Section 3 Figure 3.1 Figure 3.2 Figure 3.3 Section 4 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 MCU Operating Modes Address Map (H8S/2605)............................................................................................ 58 Address Map (H8S/2606)............................................................................................ 59 Address Map (H8S/2607)............................................................................................ 60 Exception Handling Reset Sequence (Advanced Mode with On-chip ROM Enabled)................................ 64 Reset Sequence (Advanced Mode with On-chip ROM Disabled) .............................. 65 Stack Status after Exception Handling ........................................................................ 69 Operation when SP Value Is Odd................................................................................ 70 Interrupt Controller Block Diagram of Interrupt Controller........................................................................ 72 Block Diagram of Interrupts IRQ0 to IRQ5................................................................ 80 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0...... 86 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 .................... 88 Interrupt Exception Handling...................................................................................... 90 Conflict between Interrupt Generation and Disabling................................................. 93 Rev. 1.00 Jan. 29, 2008 Page xxv of xl Section 6 PC Break Controller (PBC) Figure 6.1 Block Diagram of PC Break Controller ...................................................................... 96 Figure 6.2 Operations in Power-Down Mode Transitions.......................................................... 100 Section 7 Bus Controller (BSC) Figure 7.1 Block Diagram of Bus Controller.............................................................................. 106 Figure 7.2 Area Divisions........................................................................................................... 114 Figure 7.3 Access Sizes and Data Alignment Control (8-Bit Access Space) ............................. 117 Figure 7.4 Access Sizes and Data Alignment Control (16-bit Access Space) ............................ 118 Figure 7.5 Bus Timing for 8-Bit, 2-State Access Space ............................................................. 120 Figure 7.6 Bus Timing for 8-Bit, 3-State Access Space ............................................................. 121 Figure 7.7 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)............. 122 Figure 7.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access).............. 123 Figure 7.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) .................................. 124 Figure 7.10 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access)........... 125 Figure 7.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) ............ 126 Figure 7.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ................................ 127 Figure 7.13 Example of Wait State Insertion Timing................................................................. 128 Figure 7.14 Example of Burst ROM Access Timing (AST0 = 1 and BRSTS0 = 1) .................. 130 Figure 7.15 Example of Burst ROM Access Timing (AST0 = 0 and BRSTS1 = 0) .................. 131 Figure 7.16 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) ............ 132 Figure 7.17 Example of Idle Cycle Operation (Write after Read) .............................................. 133 Figure 7.18 Relationship between Chip Select (CS) and Read (RD) ......................................... 134 Figure 7.19 Example of Timing when Write Data Buffer Function is Used .............................. 135 Section 8 Data Transfer Controller (DTC) Figure 8.1 Block Diagram of DTC ............................................................................................. 140 Figure 8.2 Block Diagram of DTC Activation Source Control .................................................. 147 Figure 8.3 Location of DTC Register Information in Address Space......................................... 148 Figure 8.4 Flowchart of DTC Operation .................................................................................... 151 Figure 8.5 Memory Mapping in Normal Mode .......................................................................... 152 Figure 8.6 Memory Mapping in Repeat Mode ........................................................................... 153 Figure 8.7 Memory Mapping in Block Transfer Mode .............................................................. 155 Figure 8.8 Chain Transfer Operation.......................................................................................... 156 Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ..................... 157 Figure 8.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) ...................................... 158 Figure 8.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 158 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.1 Block Diagram of TPU............................................................................................ 233 Rev. 1.00 Jan. 29, 2008 Page xxvi of xl Figure 10.2 Example of Counter Operation Setting Procedure .................................................. 268 Figure 10.3 Free-Running Counter Operation ............................................................................ 269 Figure 10.4 Periodic Counter Operation..................................................................................... 270 Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match.............. 270 Figure 10.6 Example of 0 Output/1 Output Operation ............................................................... 271 Figure 10.7 Example of Toggle Output Operation ..................................................................... 271 Figure 10.8 Example of Input Capture Operation Setting Procedure ......................................... 272 Figure 10.9 Example of Input Capture Operation....................................................................... 273 Figure 10.10 Example of Synchronous Operation Setting Procedure ........................................ 274 Figure 10.11 Example of Synchronous Operation...................................................................... 275 Figure 10.12 Compare Match Buffer Operation......................................................................... 276 Figure 10.13 Input Capture Buffer Operation............................................................................. 277 Figure 10.14 Example of Buffer Operation Setting Procedure................................................... 277 Figure 10.15 Example of Buffer Operation (1) .......................................................................... 278 Figure 10.16 Example of Buffer Operation (2) .......................................................................... 279 Figure 10.17 Cascaded Operation Setting Procedure ................................................................. 280 Figure 10.18 Example of Cascaded Operation (1)...................................................................... 281 Figure 10.19 Example of Cascaded Operation (2)...................................................................... 281 Figure 10.20 Example of PWM Mode Setting Procedure .......................................................... 284 Figure 10.21 Example of PWM Mode Operation (1) ................................................................. 285 Figure 10.22 Example of PWM Mode Operation (2) ................................................................. 285 Figure 10.23 Example of PWM Mode Operation (3) ................................................................. 286 Figure 10.24 Example of Phase Counting Mode Setting Procedure........................................... 287 Figure 10.25 Example of Phase Counting Mode 1 Operation .................................................... 288 Figure 10.26 Example of Phase Counting Mode 2 Operation .................................................... 289 Figure 10.27 Example of Phase Counting Mode 3 Operation .................................................... 290 Figure 10.28 Example of Phase Counting Mode 4 Operation .................................................... 291 Figure 10.29 Phase Counting Mode Application Example......................................................... 293 Figure 10.30 Count Timing in Internal Clock Operation............................................................ 296 Figure 10.31 Count Timing in External Clock Operation .......................................................... 296 Figure 10.32 Output Compare Output Timing ........................................................................... 297 Figure 10.33 Input Capture Input Signal Timing........................................................................ 297 Figure 10.34 Counter Clear Timing (Compare Match) .............................................................. 298 Figure 10.35 Counter Clear Timing (Input Capture) .................................................................. 298 Figure 10.36 Buffer Operation Timing (Compare Match) ......................................................... 299 Figure 10.37 Buffer Operation Timing (Input Capture) ............................................................. 299 Figure 10.38 TGI Interrupt Timing (Compare Match) ............................................................... 300 Figure 10.39 TGI Interrupt Timing (Input Capture) ................................................................... 301 Figure 10.40 TCIV Interrupt Setting Timing.............................................................................. 301 Figure 10.41 TCIU Interrupt Setting Timing.............................................................................. 302 Rev. 1.00 Jan. 29, 2008 Page xxvii of xl Figure 10.42 Figure 10.43 Figure 10.44 Figure 10.45 Figure 10.46 Figure 10.47 Figure 10.48 Figure 10.49 Figure 10.50 Figure 10.51 Figure 10.52 Figure 10.53 Timing for Status Flag Clearing by CPU .............................................................. 303 Timing for Status Flag Clearing by DTC Activation ............................................ 303 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 304 Conflict between TCNT Write and Clear Operations ........................................... 305 Conflict between TCNT Write and Increment Operations.................................... 306 Conflict between TGR Write and Compare Match ............................................... 307 Conflict between Buffer Register Write and Compare Match .............................. 308 Conflict between TGR Read and Input Capture.................................................... 309 Conflict between TGR Write and Input Capture................................................... 310 Conflict between Buffer Register Write and Input Capture .................................. 311 Conflict between Overflow and Counter Clearing ................................................ 312 Conflict between TCNT Write and Overflow ....................................................... 313 Section 11 Programmable Pulse Generator (PPG) Figure 11.1 Block Diagram of PPG............................................................................................ 316 Figure 11.2 PPG Output Operation............................................................................................. 325 Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) ................................. 326 Figure 11.4 Setup Procedure for Normal Pulse Output (Example) ............................................ 327 Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output) ..................................... 328 Figure 11.6 Non-Overlapping Pulse Output ............................................................................... 329 Figure 11.7 Non-Overlapping Operation and NDR Write Timing ............................................. 330 Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example)............................. 331 Figure 11.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)................ 332 Figure 11.10 Inverted Pulse Output (Example) .......................................................................... 334 Figure 11.11 Pulse Output Triggered by Input Capture (Example)............................................ 335 Section 12 Watchdog Timer (WDT) Figure 12.1 Block Diagram of WDT_0 ...................................................................................... 338 Figure 12.2 Block Diagram of WDT_1 ...................................................................................... 338 Figure 12.3 (a) WDT_0 Operation in Watchdog Timer Mode ................................................... 345 Figure 12.3 (b) WDT_1 Operation in Watchdog Timer Mode................................................... 345 Figure 12.4 Writing to TCNT, TCSR, and RSTCSR (example for WDT0)............................... 347 Figure 12.5 Contention between TCNT Write and Increment.................................................... 348 Section 13 Serial Communication Interface (SCI) Figure 13.1 Block Diagram of SCI............................................................................................. 352 Figure 13.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 373 Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 375 Figure 13.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) ............................................................................................. 376 Figure 13.5 Sample SCI Initialization Flowchart ....................................................................... 377 Rev. 1.00 Jan. 29, 2008 Page xxviii of xl Figure 13.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 378 Figure 13.7 Sample Serial Transmission Flowchart ................................................................... 379 Figure 13.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 380 Figure 13.9 Sample Serial Reception Data Flowchart (1) .......................................................... 382 Figure 13.9 Sample Serial Reception Data Flowchart (2) .......................................................... 383 Figure 13.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) .......................................... 385 Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 387 Figure 13.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 388 Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 389 Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 390 Figure 13.14 Data Format in Synchronous Communication (For LSB-First) ............................ 391 Figure 13.15 Sample SCI Initialization Flowchart ..................................................................... 392 Figure 13.16 Sample SCI Transmission Operation in Clocked Synchronous Mode .................. 394 Figure 13.17 Sample Serial Transmission Flowchart ................................................................. 395 Figure 13.18 Example of SCI Operation in Reception ............................................................... 396 Figure 13.19 Sample Serial Reception Flowchart ...................................................................... 397 Figure 13.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ...... 399 Figure 13.21 Schematic Diagram of Smart Card Interface Pin Connections.............................. 400 Figure 13.22 Normal Smart Card Interface Data Format ........................................................... 401 Figure 13.23 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 401 Figure 13.24 Inverse Convention (SDIR = SINV = O/E = 1)..................................................... 402 Figure 13.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate)...................................................... 404 Figure 13.26 Retransfer Operation in SCI Transmit Mode ........................................................ 406 Figure 13.27 TEND Flag Generation Timing in Transmission Operation ................................. 406 Figure 13.28 Example of Transmission Processing Flow........................................................... 407 Figure 13.29 Retransfer Operation in SCI Receive Mode .......................................................... 408 Figure 13.30 Example of Reception Processing Flow................................................................ 409 Figure 13.31 Timing for Fixing Clock Output Level.................................................................. 410 Figure 13.32 Clock Halt and Restart Procedure ......................................................................... 411 Figure 13.33 Sample Transmission using DTC in Clocked Synchronous Mode........................ 417 Figure 13.34 Sample Flowchart for Mode Transition during Transmission............................... 418 Figure 13.35 Pin States during Transmission in Asynchronous Mode (Internal Clock)............. 419 Figure 13.36 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock) ..................................................................................................... 419 Figure 13.37 Sample Flowchart for Mode Transition during Reception .................................... 420 Rev. 1.00 Jan. 29, 2008 Page xxix of xl Figure 13.38 Operation when Switching from SCK Pin to Port Pin .......................................... 421 Figure 13.39 Operation when Switching from SCK Pin to Port Pin (Example of Preventing Low-Level Output) ......................................................... 422 Section 14 I2C Bus Interface Figure 14.1 Block Diagram of I2C Bus Interface........................................................................ 425 Figure 14.2 I2C Bus Interface Connections (Example: The Chip as Master) ............................ 426 Figure 14.3 I2C Bus Data Formats (I2C Bus Formats)................................................................ 448 Figure 14.4 I2C Bus Data Format (Serial Format) ...................................................................... 449 Figure 14.5 I2C Bus Timing........................................................................................................ 449 Figure 14.6 Flowchart for IIC Initialization (Example).............................................................. 450 Figure 14.7 Flowchart for Master Transmit Mode (Example).................................................... 452 Figure 14.8 (1) Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0) ..... 454 Figure 14.8 (2) Example of Master Transmit Mode Stop Condition Generation Timing (MLS = WAIT = 0)............................................................................................ 455 Figure 14.9 (1) Flowchart for Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1) (Example) ...................................................................................... 456 Figure 14.9 (2) Flowchart for Master Receive Mode (Receiving 1 Byte) (WAIT = 1) (Example) ...................................................................................... 457 Figure 14.10 (1) Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) ........................................................................ 459 Figure 14.10 (2) Example of Master Receive Mode Stop Condition Generation Timing (MLS = ACKB = 0, WAIT = 1) ........................................................................ 460 Figure 14.11 Flowcharts for Slave Transmit Mode (Example) .................................................. 461 Figure 14.12 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) ...... 463 Figure 14.13 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) ...... 464 Figure 14.14 Flowcharts for Slave Receive Mode (Example).................................................... 465 Figure 14.15 Example of Slave Transmit Mode Operation Timing (MLS = 0) ......................... 467 Figure 14.16 IRIC Setting Timing and SCL Control.................................................................. 468 Figure 14.17 Block Diagram of Noise Canceler......................................................................... 470 Figure 14.18 Points for Attention Concerning Reading of Master Receive Data....................... 477 Figure 14.19 Flowcharts and Timing of Start Condition Instruction Issuance for Retransmission................................................................................................. 478 Figure 14.20 Timing of Stop Condition Issuance....................................................................... 479 Figure 14.21 IRIC Flag Clearance in WAIT = 1 Status.............................................................. 479 Figure 14.22 ICDR Read and ICCR Access Timing in Slave Transmit Mode........................... 480 Figure 14.23 TRS Bit Setting Timing in Slave Mode ................................................................ 481 Figure 14.24 Diagram of Erroneous Operation when Arbitration is Lost .................................. 483 Figure 14.25 IRIC Flag Clear Timing when the Wait Function is Used .................................... 484 Rev. 1.00 Jan. 29, 2008 Page xxx of xl Section 15 Figure 15.1 Figure 15.2 Figure 15.3 Figure 15.4 Figure 15.5 Figure 15.6 Figure 15.7 Figure 15.8 A/D Converter Block Diagram of A/D Converter ........................................................................... 486 A/D Conversion Timing.......................................................................................... 493 External Trigger Input Timing ................................................................................ 495 A/D Conversion Precision Definitions .................................................................... 497 A/D Conversion Precision Definitions .................................................................... 497 Example of Analog Input Circuit ............................................................................ 499 Example of Analog Input Protection Circuit........................................................... 500 Analog Input Pin Equivalent Circuit ....................................................................... 501 Section 16 D/A Converter Figure 16.1 Block Diagram of D/A Converter ........................................................................... 503 Figure 16.2 D/A Converter Operation Example ......................................................................... 507 Motor Control PWM Timer (PWM) Block Diagram of PWM_1...................................................................................... 510 Block Diagram of PWM_2...................................................................................... 511 Cycle Register Compare Match............................................................................... 517 Duty Register Compare Match (OPS = 0 in PWPR_1)........................................... 519 Differences in PWM Output According to Duty Register Set Value (OPS = 0 in PWPR_1)............................................................................................. 520 Figure 17.6 Duty Register Compare Match (OPS = 0 in PWPR_2)........................................... 521 Figure 17.7 Differences in PWM Output According to Duty Register Set Value (OPS = 0 in PWPR_2)............................................................................................. 522 Figure 17.8 16-Bit Register Access Operation (Bus Master PWCYR (16 Bits)) .................. 525 Figure 17.9 8-Bit Register Access Operation (Bus Master PWCR (Upper Eight Bits))........ 525 Figure 17.10 PWM_1 Operation ................................................................................................ 526 Figure 17.11 PWM_2 Operation ................................................................................................ 527 Figure 17.12 Conflict between Buffer Register Write and Compare Match .............................. 529 Section 19 ROM Figure 19.1 Block Diagram of Flash Memory............................................................................ 534 Figure 19.2 Flash Memory State Transitions.............................................................................. 535 Figure 19.3 Boot Mode............................................................................................................... 536 Figure 19.4 User Program Mode (Example)............................................................................... 537 Figure 19.5 Flash Memory Block Configuration........................................................................ 539 Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode ........................ 550 Figure 19.7 Flowchart for Flash Memory Emulation in RAM ................................................... 551 Figure 19.8 Example of RAM Overlap Operation...................................................................... 553 Figure 19.9 Program/Program-Verify Flowchart ....................................................................... 555 Figure 19.10 Erase/Erase-Verify Flowchart ............................................................................... 557 Rev. 1.00 Jan. 29, 2008 Page xxxi of xl Section 17 Figure 17.1 Figure 17.2 Figure 17.3 Figure 17.4 Figure 17.5 Section 20 Clock Pulse Generator Figure 20.1 Block Diagram of Clock Pulse Generator ............................................................... 565 Figure 20.2 Connection of Crystal Resonator (Example)........................................................... 568 Figure 20.3 Crystal Resonator Equivalent Circuit...................................................................... 568 Figure 20.4 External Clock Input (Examples) ............................................................................ 569 Figure 20.5 External Clock Input Timing................................................................................... 570 Figure 20.6 Connection Example of 32.768-kHz Crystal Resonator.......................................... 572 Figure 20.7 Equivalent Circuit for 32.768-kHz Crystal Resonator ............................................ 572 Figure 20.8 Pin Handling when Subclock is not Used ............................................................... 573 Figure 20.9 Note on Board Design of Oscillator Circuit ............................................................ 574 Figure 20.10 External Circuitry Recommended for PLL Circuit ............................................... 574 Section 21 Figure 21.1 Figure 21.2 Figure 21.3 Figure 21.4 Power-Down Modes Mode Transition Diagram ....................................................................................... 577 Medium-Speed Mode Transition and Clearance Timing ........................................ 586 Software Standby Mode Application Example ....................................................... 588 Hardware Standby Mode Timing ............................................................................ 589 Section 23 Electrical Characteristics Figure 23.1 Output Load Circuit ................................................................................................ 632 Figure 23.2 System Clock Timing.............................................................................................. 633 Figure 23.3 Oscillator Settling Timing ....................................................................................... 634 Figure 23.4 Reset Input Timing.................................................................................................. 635 Figure 23.5 Interrupt Input Timing............................................................................................. 636 Figure 23.6 Basic Bus Timing (Two-State Access).................................................................... 638 Figure 23.7 Basic Bus Timing (Three-State Access).................................................................. 639 Figure 23.8 Basic Bus Timing (Three-State Access with One Wait State) ................................ 640 Figure 23.9 Burst ROM Access Timing (Two-State Access)..................................................... 641 Figure 23.10 Burst ROM Access Timing (One-State Access) ................................................... 642 Figure 23.11 I/O Port Input/Output Timing (Ports 1, 3, 4, 9, A to F)......................................... 644 Figure 23.12 I/O Port (Ports H and J) Input/Output Timing....................................................... 644 Figure 23.13 PPG Output Timing............................................................................................... 645 Figure 23.14 TPU Input/Output Timing ..................................................................................... 645 Figure 23.15 TPU Clock Input Timing....................................................................................... 645 Figure 23.16 Motor Control PWM Output Timing .................................................................... 646 Figure 23.17 SCK Clock Input Timing ...................................................................................... 646 Figure 23.18 SCI Input/Output Timing (Clock Synchronous Mode) ......................................... 646 Figure 23.19 A/D Converter External Trigger Input Timing...................................................... 646 Figure 23.20 I2C Bus Interface Input/Output Timing ................................................................. 648 Rev. 1.00 Jan. 29, 2008 Page xxxii of xl Appendix Figure C.1 FP-128B Package Dimensions ................................................................................. 659 Rev. 1.00 Jan. 29, 2008 Page xxxiii of xl Rev. 1.00 Jan. 29, 2008 Page xxxiv of xl Tables Section 1 Overview Table 1.1 Pin Functions in Each Operating Mode .................................................................... 5 Table 1.2 Pin Functions .......................................................................................................... 10 Section 2 CPU Table 2.1 Instruction Classification ........................................................................................ 31 Table 2.2 Operation Notation ................................................................................................. 32 Table 2.3 Data Transfer Instructions ...................................................................................... 33 Table 2.4 Arithmetic Operations Instructions (1) ................................................................... 34 Table 2.4 Arithmetic Operations Instructions (2) ................................................................... 35 Table 2.5 Logic Operations Instructions................................................................................. 36 Table 2.6 Shift Instructions..................................................................................................... 36 Table 2.7 Bit Manipulation Instructions (1)............................................................................ 37 Table 2.7 Bit Manipulation Instructions (2)............................................................................ 38 Table 2.8 Branch Instructions ................................................................................................. 39 Table 2.9 System Control Instructions.................................................................................... 40 Table 2.10 Block Data Transfer Instructions ............................................................................ 41 Table 2.11 Addressing Modes .................................................................................................. 43 Table 2.12 Absolute Address Access Ranges........................................................................... 45 Table 2.13 Effective Address Calculation (1)........................................................................... 47 Table 2.13 Effective Address Calculation (2)........................................................................... 48 Section 3 MCU Operating Modes Table 3.1 MCU Operating Mode Selection ............................................................................ 53 Table 3.2 Pin Functions in Each Mode ................................................................................... 57 Section 4 Exception Handling Table 4.1 Exception Types and Priority.................................................................................. 61 Table 4.2 Exception Handling Vector Table .......................................................................... 62 Table 4.3 Statuses of CCR and EXR after Trace Exception Handling ................................... 67 Table 4.4 Statuses of CCR and EXR after Trap Instruction Exception Handling .................. 68 Section 5 Interrupt Controller Table 5.1 Pin Configuration.................................................................................................... 73 Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................ 82 Table 5.3 Interrupt Control Modes ......................................................................................... 85 Table 5.4 Interrupt Response Times ....................................................................................... 91 Table 5.5 Number of States in Interrupt Handling Routine Execution Status ........................ 92 Rev. 1.00 Jan. 29, 2008 Page xxxv of xl Section 7 Bus Controller (BSC) Table 7.1 Pin Configuration.................................................................................................. 107 Table 7.2 Bus Specifications for Each Area (Basic Bus Interface)....................................... 116 Table 7.3 Data Buses Used and Valid Strobes...................................................................... 119 Table 7.4 Pin States in Idle Cycle......................................................................................... 134 Section 8 Data Transfer Controller (DTC) Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs .............. 149 Table 8.2 Register Information in Normal Mode.................................................................. 152 Table 8.3 Register Information in Repeat Mode................................................................... 153 Table 8.4 Register Information in Block Transfer Mode...................................................... 154 Table 8.5 DTC Execution Status .......................................................................................... 159 Table 8.6 Number of States Required for Each Execution Status......................................... 159 Section 9 I/O Ports Table 9.1 Port Functions....................................................................................................... 166 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 TPU Functions ...................................................................................................... 230 Table 10.2 TPU Pins............................................................................................................... 234 Table 10.3 CCLR0 to CCLR2 (Channels 0 and 3) ................................................................. 238 Table 10.4 CCLR0 to CCLR2 (Channels 1, 2, 4, and 5) ........................................................ 238 Table 10.5 TPSC0 to TPSC2 (Channel 0) .............................................................................. 239 Table 10.6 TPSC0 to TPSC2 (Channel 1) .............................................................................. 239 Table 10.7 TPSC0 to TPSC2 (Channel 2) .............................................................................. 240 Table 10.8 TPSC0 to TPSC2 (Channel 3) .............................................................................. 240 Table 10.9 TPSC0 to TPSC2 (Channel 4) .............................................................................. 241 Table 10.10 TPSC0 to TPSC2 (Channel 5) .......................................................................... 241 Table 10.11 MD0 to MD3 .................................................................................................... 243 Table 10.12 TIORH_0 (Channel 0) ...................................................................................... 245 Table 10.13 TIORL_0 (Channel 0)....................................................................................... 246 Table 10.14 TIOR_1 (Channel 1) ......................................................................................... 247 Table 10.15 TIOR_2 (Channel 2) ......................................................................................... 248 Table 10.16 TIORH_3 (Channel 3) ...................................................................................... 249 Table 10.17 TIORL_3 (Channel 3)....................................................................................... 250 Table 10.18 TIOR_4 (Channel 4) ......................................................................................... 251 Table 10.19 TIOR_5 (Channel 5) ......................................................................................... 252 Table 10.20 TIORH_0 (Channel 0) ...................................................................................... 253 Table 10.21 TIORL_0 (Channel 0)....................................................................................... 254 Table 10.22 TIOR_1 (Channel 1) ......................................................................................... 255 Table 10.23 TIOR_2 (Channel 2) ......................................................................................... 256 Rev. 1.00 Jan. 29, 2008 Page xxxvi of xl Table 10.24 Table 10.25 Table 10.26 Table 10.27 Table 10.28 Table 10.29 Table 10.30 Table 10.31 Table 10.32 Table 10.33 Table 10.34 Table 10.35 Table 10.36 TIORH_3 (Channel 3) ...................................................................................... 257 TIORL_3 (Channel 3)....................................................................................... 258 TIOR_4 (Channel 4) ......................................................................................... 259 TIOR_5 (Channel 5) ......................................................................................... 260 Register Combinations in Buffer Operation ..................................................... 276 Cascaded Combinations.................................................................................... 280 PWM Output Registers and Output Pins .......................................................... 283 Phase Counting Mode Clock Input Pins ........................................................... 287 Up/Down-Count Conditions in Phase Counting Mode 1.................................. 288 Up/Down-Count Conditions in Phase Counting Mode 2.................................. 289 Up/Down-Count Conditions in Phase Counting Mode 3.................................. 290 Up/Down-Count Conditions in Phase Counting Mode 4.................................. 291 TPU Interrupts .................................................................................................. 294 Section 11 Programmable Pulse Generator (PPG) Table 11.1 Pin Configuration.................................................................................................. 317 Section 12 Watchdog Timer (WDT) Table 12.1 WDT Interrupt Sources......................................................................................... 346 Section 13 Serial Communication Interface (SCI) Table 13.1 Pin Configuration.................................................................................................. 353 Table 13.2 The Relationships between The N Setting in BRR and Bit Rate B ...................... 366 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ........................... 367 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ........................... 368 Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ........................... 369 Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 369 Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 370 Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 371 Table 13.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 371 Table 13.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When n = 0 and S = 372)...................................... 372 Table 13.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) ...................................................... 372 Table 13.10 Serial Transfer Formats (Asynchronous Mode).................................................... 374 Table 13.11 SSR Status Flags and Receive Data Handling ...................................................... 381 Table 13.12 SCI Interrupt Sources............................................................................................ 413 Table 13.13 SCI Interrupt Sources............................................................................................ 414 Section 14 I2C Bus Interface Table 14.1 I2C Bus Interface Pins........................................................................................... 426 Table 14.2 Transfer Format .................................................................................................... 431 Rev. 1.00 Jan. 29, 2008 Page xxxvii of xl Table 14.3 Table 14.4 Table 14.5 Table 14.6 Table 14.7 Table 14.8 Table 14.9 I2C Transfer Rate .................................................................................................. 434 Flags and Transfer States...................................................................................... 441 I2C Bus Data Format Symbols.............................................................................. 449 Examples of Operation Using the DTC ................................................................ 469 I2C Bus Timing (SCL and SDA Output) .............................................................. 472 Permissible SCL Rise Time (tSr) Values............................................................... 473 I2C Bus Timing (with Maximum Influence of tSr/tSf)............................................ 475 Section 15 A/D Converter Table 15.1 Pin Configuration.................................................................................................. 487 Table 15.2 Analog Input Channels and Corresponding ADDR Registers .............................. 488 Table 15.3 A/D Conversion Time (Single Mode)................................................................... 494 Table 15.4 A/D Conversion Time (Scan Mode) ..................................................................... 494 Table 15.5 A/D Converter Interrupt Source............................................................................ 495 Table 15.6 Analog Pin Specifications..................................................................................... 501 Section 16 D/A Converter Table 16.1 Pin Configuration.................................................................................................. 504 Table 16.2 D/A Channel Enable ............................................................................................. 506 Section 17 Motor Control PWM Timer (PWM) Table 17.1 Pin Configuration.................................................................................................. 512 Table 17.2 Output Selection by OTS Bit ................................................................................ 519 Table 17.3 Output Selection by TDS Bit ................................................................................ 524 Section 19 ROM Table 19.1 Differences between Boot Mode and User Program Mode .................................. 535 Table 19.2 Pin Configuration.................................................................................................. 540 Table 19.3 Setting On-Board Programming Modes ............................................................... 547 Table 19.4 Boot Mode Operation ........................................................................................... 549 Table 19.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible ........................................................................................ 549 Table 19.6 Flash Memory Operating States............................................................................ 560 Table 19.7 Registers Present in F-ZTAT Version but Absent in Mask ROM Version........... 563 Section 20 Clock Pulse Generator Table 20.1 Damping Resistance Value ................................................................................... 568 Table 20.2 Crystal Resonator Characteristics ......................................................................... 569 Table 20.3 External Clock Input Conditions .......................................................................... 570 Section 21 Power-Down Modes Table 21.1 LSI Internal States in Each Mode ......................................................................... 576 Table 21.2 Power-Down Mode Transition Conditions ........................................................... 578 Rev. 1.00 Jan. 29, 2008 Page xxxviii of xl Table 21.3 Standby Time Settings .......................................................................................... 581 Section 23 Electrical Characteristics Table 23.1 Absolute Maximum Ratings ................................................................................. 625 Table 23.2 DC Characteristics ................................................................................................ 626 Table 23.3 Permissible Output Currents ................................................................................. 630 Table 23.4 Bus Drive Characteristics ..................................................................................... 631 Table 23.5 Clock Timing ........................................................................................................ 633 Table 23.6 Control Signal Timing .......................................................................................... 635 Table 23.7 Bus Timing ........................................................................................................... 637 Table 23.8 Timing of On-Chip Supporting Modules.............................................................. 643 Table 23.9 I2C Bus Interface Timing ...................................................................................... 647 Table 23.10 A/D Conversion Characteristics............................................................................ 649 Table 23.11 D/A Conversion Characteristics............................................................................ 650 Table 23.12 Flash Memory Characteristics .............................................................................. 651 Rev. 1.00 Jan. 29, 2008 Page xxxix of xl Rev. 1.00 Jan. 29, 2008 Page xl of xl Section 1 Overview Section 1 Overview 1.1 Features * High-speed H8S/2600 central processing unit with 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers Sixty-nine basic instructions * Various peripheral functions PC break controller (PBC) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG) Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface (SCI) I2C bus interface (IIC) Motor control PWM timer 10-bit A/D converter 8-bit D/A converter Clock pulse generator * On-chip memory ROM Flash memory version Masked ROM version Product Code HD64F2607 HD6432607 HD6432606 HD6432605 ROM 384 kbytes 384 kbytes 256 kbytes 128 kbytes RAM 16 kbytes 16 kbytes 16 kbytes 16 kbytes Remarks * General I/O ports I/O pins: 72 Input pins: 12 * Supports various power-down modes Rev. 1.00 Jan. 29, 2008 Page 1 of 666 REJ09B0427-0100 Section 1 Overview * Compact package Package 128-pin QFP Code FP-128B/FP-128BV Body Size 14.0 x 20.0 mm Pin Pitch 0.5 mm Rev. 1.00 Jan. 29, 2008 Page 2 of 666 REJ09B0427-0100 Section 1 Overview 1.2 Block Diagram Figure 1.1 shows a block diagram. PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Port D Interrupt controller PC break controller Port F TPU D/A converter A/D converter PJ0/PWM2A PJ1/PWM2B PJ2/PWM2C PJ3/PWM2D PJ4/PWM2E PJ5/PWM2F PJ6/PWM2G PJ7/PWM2H Port J PPG P93/AN11 P92/AN10 P91/AN9 P90/AN8 Port 1 Port 4 P47 / AN7/ DA1 P46 / AN6/ DA0 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 P10 / PO8/ TIOCA0 /A20 P11 / PO9/ TIOCB0 /A21 P12 / PO10/ TIOCC0 / TCLKA/A22 P13 / PO11/ TIOCD0 / TCLKB/A23 P14 / PO12/ TIOCA1/IRQ0 P15 / PO13/ TIOCB1 / TCLKC P16 / PO14/ TIOCA2/IRQ1 P17 / PO15/ TIOCB2 / TCLKD PWMVCC PWMVCC PWMVSS PWMVSS PWMVSS Notes: 1. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the U-mask version. These functions cannot be used with the other versions. See section 20.6, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2. 2. The FWE pin only applies to the flash memory version. The FWE pin is a NC pin in the mask ROM versions. In the mask ROM version, the FWE pin must be left open or be connected to Vss. Figure 1.1 Block Diagram Vref AVCC AVSS Rev. 1.00 Jan. 29, 2008 Page 3 of 666 REJ09B0427-0100 Port 9 Port 3 PH0/PWM1A PH1/PWM1B PH2/PWM1C PH3/PWM1D PH4/PWM1E PH5/PWM1F PH6/PWM1G PH7/PWM1H WDT x 2 channels Port H RAM SCI x 3 channels Motor control PWM timer Port C PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF0/IRQ2 Peripheral data bus DTC Peripheral address bus VCL MD2 MD1 MD0 OSC2 OSC1 EXTAL XTAL PLLCAP STBY RES NMI FWE* PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 Port E H8S/2600 CPU Internal data bus Internal address bus Clock pulse generator PA3/A19/SCK2 PA2/A18/RxD2 PA1/A17/TxD2 PA0/A16 Bus controller Port A PLL PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3 / A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TIOCA3 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 ROM (flash memory, mask ROM) Port B P35/SCK1/IRQ5 P34/RxD1 P33/TxD1 P32/SCK0/IRQ4 P31/RxD0 P30/TxD0 Section 1 Overview 1.3 1.3.1 Pin Assignments Pin Assignments Figure 1.2 shows pin assignments. Vref AVCC NC VSS NC NC P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/IRQ1 P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/TCLKB/A23 P12/PO10/TIOCC0/TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20 PF7/ STBY FWE*2 EXTAL *1 VSS 0.1 F XTAL VCL VCC VCC OSC1*2 OSC2*2 PLLVSS VSS PLLCAP NMI RES P35/SCK1/SCL0/IRQ5 P34/RxD1/SDA0 P33/TxD1/SCL1 P32/SCK0/SDA1/IRQ4 VSS VSS P31/RxD0 P30/TxD0 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 Rev. 1.00 Jan. 29, 2008 Page 4 of 666 REJ09B0427-0100 VCC VCC NC NC PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 VCC PD0/D8 VSS PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 VSS VSS NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 P47/AN7/DA1 P90/AN8 P91/AN9 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 H8S/2607 Group PRQP0128KB-A FP-128B/FP-128BV (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 PWMVSS PJ7/PWM2H PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E PWMVCC PJ3/PWM2D PJ2/PWM2C PJ1/PWM2B PJ0/PWM2A PWMVSS PH7/PWM1H PH6/PWM1G PH5/PWM1F PH4/PWM1E PWMVCC PH3/PWM1D PH2/PWM1C PH1/PWM1B PH0/PWM1A PWMVSS VSS PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS Figure 1.2 Pin Assignments Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.1 shows the pin functions in each of the operating modes. Table 1.1 Pin Functions in Each Operating Mode Pin Name Pin No. Mode 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VCC VCC NC NC PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 VCC D8 VSS Mode 5 VCC VCC NC NC PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 VCC D8 VSS Mode 6 VCC VCC NC NC PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 D15 D14 D13 D12 D11 D10 D9 VCC D8 VSS Mode 7 VCC VCC NC NC PA0 PA1/TxD2 PA2/RxD2 PA3/SCK2 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 VCC PD0 VSS Rev. 1.00 Jan. 29, 2008 Page 5 of 666 REJ09B0427-0100 Section 1 Overview Pin Name Pin No. Mode 4 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 VSS VSS NC NC AS RD HWR LWR/ADTRG/ IRQ3 VSS PWMVSS PH0/PWM1A PH1/PWM1B PH2/PWM1C PH3/PWM1D PWMVCC PH4/PWM1E PH5/PWM1F PH6/PWM1G PH7/PWM1H PWMVSS PJ0/PWM2A PJ1/PWM2B Mode 5 PE7/D7 PE6/D6 PE5/D5 PB0/A8 PE3/D3 PE2/D2 PE1/D1 PE0/D0 VSS VSS NC NC AS RD HWR PF3/LWR/ADTRG/ IRQ3 VSS PWMVSS PH0/PWM1A PH1/PWM1B PH2/PWM1C PH3/PWM1D PWMVCC PH4/PWM1E PH5/PWM1F PH6/PWM1G PH7/PWM1H PWMVSS PJ0/PWM2A PJ1/PWM2B Mode 6 PE7/D7 PE6/D6 PE5/D5 PB0/A8 PE3/D3 PE2/D2 PE1/D1 PE0/D0 VSS VSS NC NC AS RD HWR PF3/LWR/ADTRG/ IRQ3 VSS PWMVSS PH0/PWM1A PH1/PWM1B PH2/PWM1C PH3/PWM1D PWMVCC PH4/PWM1E PH5/PWM1F PH6/PWM1G PH7/PWM1H PWMVSS PJ0/PWM2A PJ1/PWM2B Mode 7 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 VSS VSS NC NC PF6 PF5 PF4 PF3/ ADTRG/ IRQ3 VSS PWMVSS PH0/PWM1A PH1/PWM1B PH2/PWM1C PH3/PWM1D PWMVCC PH4/PWM1E PH5/PWM1F PH6/PWM1G PH7/PWM1H PWMVSS PJ0/PWM2A PJ1/PWM2B Rev. 1.00 Jan. 29, 2008 Page 6 of 666 REJ09B0427-0100 Section 1 Overview Pin Name Pin No. Mode 4 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 PJ2/PWM2C PJ3/PWM2D PWMVCC PJ4/PWM2E PJ5/PWM2F PJ6/PWM2G PJ7/PWM2H PJ2/PWM2C PJ3/PWM2D PWMVcc VSS VSS P32/SCK0/SDA1/ IRQ4 P33/TxD1/SCL1 P34/RxD1/SDA0 P35/SCK1/SCL0/ IRQ5 RES NMI PLLCAP VSS PLLVSS OSC2 OSC1 VCC VCC VCL XTAL VSS Mode 5 PJ2/PWM2C PJ3/PWM2D PWMVCC PJ4/PWM2E PJ5/PWM2F PJ6/PWM2G PJ7/PWM2H PJ2/PWM2C PJ3/PWM2D PWMVcc VSS VSS P32/SCK0/SDA1/ IRQ4 P33/TxD1/SCL1 P34/RxD1/SDA0 P35/SCK1/SCL0/ IRQ5 RES NMI PLLCAP VSS PLLVSS OSC2 OSC1 VCC VCC VCL XTAL VSS Mode 6 PJ2/PWM2C PJ3/PWM2D PWMVCC PJ4/PWM2E PJ5/PWM2F PJ6/PWM2G PJ7/PWM2H PJ2/PWM2C PJ3/PWM2D PWMVcc VSS VSS P32/SCK0/SDA1/ IRQ4 P33/TxD1/SCL1 P34/RxD1/SDA0 P35/SCK1/SCL0/ IRQ5 RES NMI PLLCAP VSS PLLVSS OSC2 OSC1 VCC VCC VCL XTAL VSS Mode 7 PJ2/PWM2C PJ3/PWM2D PWMVCC PJ4/PWM2E PJ5/PWM2F PJ6/PWM2G PJ7/PWM2H PJ2/PWM2C PJ3/PWM2D PWMVcc VSS VSS P32/SCK0/SDA1/ IRQ4 P33/TxD1/SCL1 P34/RxD1/SDA0 P35/SCK1/SCL0/ IRQ5 RES NMI PLLCAP VSS PLLVSS OSC2 OSC1 VCC VCC VCL XTAL VSS Rev. 1.00 Jan. 29, 2008 Page 7 of 666 REJ09B0427-0100 Section 1 Overview Pin Name Pin No. Mode 4 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 XTAL FEW* STBY PF7/ P10/PO8/TIOCA0/ A20 P11/PO9/TIOCB0/ A21 P12/PO10/TIOCC0/ TCLKA/A22 P13/PO11/TIOCD0/ TCLKB/A23 P14/PO12/TIOCA1/ IRQ0 P15/PO13/TIOCB1/ TCLKC P16/PO14/TIOCA2/ IRQ1 P17/PO15/TIOCB2/ TCLKD NC NC VSS NC AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 Mode 5 XTAL FEW* STBY PF7/ P10/PO8/TIOCA0/ A20 P11/PO9/TIOCB0/ A21 P12/PO10/TIOCC0/ TCLKA/A22 P13/PO11/TIOCD0/ TCLKB/A23 P14/PO12/TIOCA1/ IRQ0 P15/PO13/TIOCB1/ TCLKC P16/PO14/TIOCA2/ IRQ1 P17/PO15/TIOCB2/ TCLKD NC NC VSS NC AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 Mode 6 XTAL FEW* STBY PF7/ P10/PO8/TIOCA0/ A20 P11/PO9/TIOCB0/ A21 P12/PO10/TIOCC0/ TCLKA/A22 P13/PO11/TIOCD0/ TCLKB/A23 P14/PO12/TIOCA1/ IRQ0 P15/PO13/TIOCB1/ TCLKC P16/PO14/TIOCA2/ IRQ1 P17/PO15/TIOCB2/ TCLKD NC NC VSS NC AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 Mode 7 XTAL FEW* STBY PF7/ P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/ TCLKA P13/PO11/TIOCD0/ TCLKB P14/PO12/TIOCA1/ IRQ0 P15/PO13/TIOCB1/ TCLKC P16/PO14/TIOCA2/ IRQ1 P17/PO15/TIOCB2/ TCLKD NC NC VSS NC AVCC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/DA0 Rev. 1.00 Jan. 29, 2008 Page 8 of 666 REJ09B0427-0100 Section 1 Overview Pin Name Pin No. Mode 4 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 P47/AN7/DA1 P90/AN8 P91/AN9 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 Mode 5 P47/AN7/DA1 P90/AN8 P91/AN9 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 Mode 6 P47/AN7/DA1 P90/AN8 P91/AN9 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 Mode 7 P47/AN7/DA1 P90/AN8 P91/AN9 P92/AN10 P93/AN11 AVSS MD0 MD1 MD2 PF0/IRQ2 PB7/A15/TIOCB5 PB6/A14/TIOCA5 PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 VSS PB0/A8/TIOCA3 Notes: The NC pins should be connected to VSS, or left open. * The FEW pin is only for Flash memory version, and functions as an NC pin for Mask ROM version. For Mask ROM version, this pin should be left open or connected to VSS Rev. 1.00 Jan. 29, 2008 Page 9 of 666 REJ09B0427-0100 Section 1 Overview 1.3.3 Pin Functions Table 1.2 shows pin functions. Table 1.2 Type Power supply Pin Functions Symbol Vcc Pin No. I/O Name and Function Power supply pins These pins should be connected to the system power supply. Vss 26, 35, 36, Input 43, 67, 68, 76, 84, 99, 127 82 Output Ground pins These pins should be connected to the system power supply (0 V). 1, 2, 24, 81 Input VCL Connect to Vss via a 0.1 F capacitor (which should be located near the pin). Do not connect this pin to an external power supply. Ground pin for on-chip PLL oscillator External capacitance pin for on-chip PLL oscillator Connects to a crystal oscillator. See section 20, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator. The EXTAL pin can also input an external clock. Clock PLLVss PLLCAP XTAL EXTAL 77 75 83 85 Input Input Input Input OSC1 OSC2 79 78 Input Input Connects to a 32.768-kHz crystal oscillator. See section 20, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator. Supplies the system clock to an external device. 88 Output Rev. 1.00 Jan. 29, 2008 Page 10 of 666 REJ09B0427-0100 Section 1 Overview Type Operating mode control System control Symbol MD2 to MD0 RES Pin No. I/O Name and Function These pins set the operating mode. These pins should not be changed while this LSI is operating. 118 to 116 Input 73 Input Reset pin When this pin is driven low, the chip is reset. STBY FEW* Interrupts NMI 87 86 74 Input Input Input When this pin is driven low, a transition is made to hardware standby mode. Pin for flash memory Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. These pins request a maskable interrupt. These pins output an address. IRQ5 to IRQ0 Address bus A23 to A0 72, 69, 42, Input 119, 95, 93 92 to 89, Output 8 to 5, 120 to 126, 128, 9 to 16 17 to 23, 25, 27 to 34 39 I/O Data bus D15 to D0 These pins constitute a bidirectional data bus. When this pin is low, it indicates that address output on the address bus is enabled. When this pin is low, it indicates that the external address space can be read. A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. Bus control AS Output RD HWR 40 41 Output Output LWR 42 Output Rev. 1.00 Jan. 29, 2008 Page 11 of 666 REJ09B0427-0100 Section 1 Overview Type 16-bit timer pulse unit (TPU) Symbol TCLKD to TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, TIOCB5 Pin No. I/O Name and Function These pins input an external clock. TGR0A to TGR0D input capture input, output compare output, or output PWM. 96, 94, 92, Input 91 89 90 91 92 93 94 95 96 128 126 125 124 123 122 121 120 96 to 89 6 70 65 7 71 66 8 72 69 I/O I/O I/O I/O TGR1A and TGR1B input capture input, output compare output, or output PWM. TGR2A and TGR2B input capture input, output compare output, or output PWM. TGR3A to TGR3D input capture input, output compare output, or output PWM. I/O I/O Output Output TGR4A and TGR4B input capture input, output compare output, or output PWM. TGR5A and TGR5B input capture input, output compare output, or output PWM. Pulse output pins Transmit data output pins Programmable pulse PO15 to generator (PPG) PO8 Serial communication TxD2, interface (SCI)/ TxD1, Smart Card interface TxD0 RxD2, RxD1, RxD0 SCK2, SCK1, SCK0 Input Receive data input pins I/O Clock I/O pins Rev. 1.00 Jan. 29, 2008 Page 12 of 666 REJ09B0427-0100 Section 1 Overview Type 2 Symbol Pin No. 72 70 71 69 I/O I/O Name and Function I2C clock I/O pins that can drive the bus The output type of SCL0 is NMOS opendrain. I C bus interface (IIC) SCL0 SCL1 SDA0 SDA1 A/D converter AN11 to AN0 ADTRG D/A converter A/D converter/ D/A converter DA1 DA0 AVcc I/O I C data I/O pins that can drive the bus The output type of SDA0 is NMOS opendrain. Analog input pins Pin for input of an external trigger to start A/D conversion D/A converter analog output pins Power supply pin for A/D converter or D/A converter If the A/D converter or D/A converter is not used, connect this pin to the system power supply (+5 V). 2 114 to 103 Input 42 110 109 101 Input Output Input AVss 115 Input Ground pin for for A/D converter or D/A converter Connect this pin to the system power supply (0 V). Vref 102 Input Reference voltage input pin for A/D converter or D/A converter If the A/D converter is not used, connect this pin to the system power supply (+5 V). Motor control PWM timer PWM1A to 53 to 50, PWM1H 48 to 45 PWM2A to 63 to 60, PWM2H 58 to 55 PWMVCC 49, 59 Output Output Input Motor control PWM timer channel 1 output pins Motor control PWM timer channel 2 output pins Motor control PWM power supply pins If the motor control is not used, connect these pins to the system power supply (+5V). PWMVSS 44, 54, 64 Input Motor control PWM ground pins Connect these pins to the system power supply (0V). Rev. 1.00 Jan. 29, 2008 Page 13 of 666 REJ09B0427-0100 Section 1 Overview Type I/O ports Symbol Pin No. I/O I/O I/O Name and Function 8-bit I/O pins 6-bit I/O pins 8-bit I/O pins 4-bit input pins 4-bit I/O pins 8-bit I/O pins 8-bit I/O pins 8-bit I/O pins 8-bit I/O pins 6-bit I/O pins P17 to P10 96 to 89 P35 to P30 72 to 69, 66, 65 P47 to P40 110 to 103 Input P93 to P90 114 to 111 Input PA3 to PA0 PB7 to PB0 PC7 to PC0 PD7 to PD0 PE7 to PE0 PF7 to PF2, PF0 PH7 to PH0 8 to 5 I/O 120 to 126, I/O 128 9 to 16 17 to 23, 25 27 to 34 88, 39 to 42, 119 53 to 50, 48 to 45 I/O I/O I/O I/O I/O I/O 8-bit I/O pins 8-bit I/O pins PJ7 to PJ0 63 to 60, 58 to 55 Note: * The FEW pin is only for Flash memory version, and functions as an NC pin for Mask ROM version. For Mask ROM version, this pin should be left open or connected to VSS. Rev. 1.00 Jan. 29, 2008 Page 14 of 666 REJ09B0427-0100 Section 2 CPU Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.1 Features * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H CPUs object programs * General-register architecture Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers * Sixty-nine basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16, ERn) or @(d:32, ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes * High-speed operation All frequently-used instructions execute in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 3 states Rev. 1.00 Jan. 29, 2008 Page 15 of 666 REJ09B0427-0100 Section 2 CPU 16 / 8-bit register-register divide: 12 states 16 x 16-bit register-register multiply: 4 states 32 / 16-bit register-register divide: 20 states * Two CPU operating modes Normal mode* Advanced mode * Power-down state Transition to power-down state by the SLEEP instruction CPU clock speed selection Note: * Normal mode is not available in this LSI. 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are shown below. * Register configuration The MAC register is supported by the H8S/2600 CPU only. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by the H8S/2600 CPU only. * The number of execution states of the MULXU and MULXS instructions; Execution States Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 In addition, there are differences in address space, CCR and EXR register functions, and powerdown modes, etc., depending on the model. Rev. 1.00 Jan. 29, 2008 Page 16 of 666 REJ09B0427-0100 Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements: * More general registers and control registers Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements: * More control registers One 8-bit and two 32-bit control registers have been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. A multiply-and-accumulate instruction has been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. Rev. 1.00 Jan. 29, 2008 Page 17 of 666 REJ09B0427-0100 Section 2 CPU * Higher speed Basic instructions execute twice as fast. 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. * Address Space Linear access to a 64-kbyte maximum address space is provided. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. * Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The exception vector table structure in normal mode is shown in figure 2.1. For details of the exception vector table, see section 4, Exception Handling. The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. Branch addresses can be stored in the area from H'0000 to H'00FF. Note that the first part of this range is also used for the exception vector table. Rev. 1.00 Jan. 29, 2008 Page 18 of 666 REJ09B0427-0100 Section 2 CPU * Stack Structure When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. Note: Normal mode is not available in this LSI. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Exception vector 1 Exception vector 2 Exception vector 3 Exception vector 4 Exception vector 5 Exception vector 6 Exception vector table Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) SP (SP * 2 EXR*1 Reserved*1,*3 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. lgnored when returning. (b) Exception Handling Figure 2.2 Stack Structure in Normal Mode Rev. 1.00 Jan. 29, 2008 Page 19 of 666 REJ09B0427-0100 Section 2 CPU 2.2.2 Advanced Mode * Address Space Linear access to a 16-Mbyte maximum address space is provided. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Exception vector 1 H'00000003 H'00000004 Reserved Exception vector 2 H'00000007 H'00000008 Reserved Exception vector table Exception vector 3 H'0000000B H'0000000C Reserved Exception vector 4 H'00000010 Reserved Exception vector 5 Figure 2.3 Exception Vector Table (Advanced Mode) Rev. 1.00 Jan. 29, 2008 Page 20 of 666 REJ09B0427-0100 Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also used for the exception vector table. * Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) (SP *2 ) EXR*1 Reserved*1, *3 CCR PC (24 bits) (a) Subroutine Branch Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. (b) Exception Handling Figure 2.4 Stack Structure in Advanced Mode Rev. 1.00 Jan. 29, 2008 Page 21 of 666 REJ09B0427-0100 Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. H'0000 64-kbyte H'FFFF H'00000000 16-Mbyte Program area H'00FFFFFF Data area Cannot be used in this LSI H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Figure 2.5 Memory Map Rev. 1.00 Jan. 29, 2008 Page 22 of 666 REJ09B0427-0100 Section 2 CPU 2.4 Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate register (MAC). General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Control Registers (CR) 23 PC 0 EXR T 76543210 - - - - I2 I1 I0 76543210 CCR I UI H U N Z V C 63 MAC 31 [Legend] SP: PC: EXR: T: I2 to I0: CCR: I: UI: Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit H: U: N: Z: V: C: MAC: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply-accumulate register Sign extension MACL 0 41 MACH 32 Figure 2.6 CPU Registers Rev. 1.00 Jan. 29, 2008 Page 23 of 666 REJ09B0427-0100 Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8bit registers. The usage of each register can be selected independently. General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the stack. * Address registers * 32-bit registers * 16-bit registers * 8-bit registers E registers (extended registers) (E0 to E7) ER registers (ER0 to ER7) R registers (R0 to R7) RL registers (R0L to R7L) RH registers (R0H to R7H) Figure 2.7 Usage of General Registers Rev. 1.00 Jan. 29, 2008 Page 24 of 666 REJ09B0427-0100 Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0). 2.4.3 Extended Control Register (EXR) EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions. When these instructions, except for the STC instruction, are executed, all interrupts including NMI will be masked for three states after execution is completed. Bit 7 Bit Name T Initial Value 0 R/W R/W Description Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 2 1 0 I2 I1 I0 All 1 1 1 1 R/W R/W R/W Reserved These bits are always read as 1. These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Rev. 1.00 Jan. 29, 2008 Page 25 of 666 REJ09B0427-0100 Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be read or written by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit cannot be used as an interrupt mask bit in this LSI. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be read or written by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit of data as a sign bit. 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Rev. 1.00 Jan. 29, 2008 Page 26 of 666 REJ09B0427-0100 Section 2 CPU Bit 1 Bit Name V Initial Value R/W Description Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Undefined R/W 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * * * Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.5 Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are a sign extension. 2.4.6 Initial Values of CPU Registers Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev. 1.00 Jan. 29, 2008 Page 27 of 666 REJ09B0427-0100 Section 2 CPU 2.5 Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers. Data Type 1-bit data Register Number RnH Data Format 7 0 Don't care 76 54 32 10 7 1-bit data RnL Don't care 0 76 54 32 10 7 4-bit BCD data RnH Upper 43 Lower 0 Don't care 7 4-bit BCD data RnL Don't care Upper 43 Lower 0 7 Byte data RnH MSB 0 Don't care LSB 7 0 LSB Byte data RnL Don't care MSB Figure 2.9 General Register Data Formats (1) Rev. 1.00 Jan. 29, 2008 Page 28 of 666 REJ09B0427-0100 Section 2 CPU Data Type Word data Register Number Rn Data Format 15 0 MSB LSB Word data 15 En 0 MSB LSB Longword data 31 ERn 16 15 0 MSB En Rn LSB [Legend] ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 1.00 Jan. 29, 2008 Page 29 of 666 REJ09B0427-0100 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches. When ER7 is used as an address register to access the stack, the operand size should be word or longword. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 Data Format 0 0 Byte data Address L MSB LSB Word data Address 2M Address 2M+1 MSB LSB Longword data Address 2N Address 2N+1 Address 2N+2 Address 2N+3 MSB LSB Figure 2.10 Memory Data Formats Rev. 1.00 Jan. 29, 2008 Page 30 of 666 REJ09B0427-0100 Section 2 CPU 2.6 Instruction Set The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1. Table 2.1 Function Data transfer Instruction Classification Instructions MOV POP* , PUSH* LDM, STM MOVFPE* , MOVTPE* 3 3 1 1 Size Types B/W/L 5 W/L L B B/W/L 23 B B/W/L L B/W W/L B B/W/L 4 Arithmetic operation ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS* 4 MAC, LDMAC, STMAC, CLRMAC Logic operations Shift Bit manipulation Branch System control AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L 8 BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc*2, JMP, BSR, JSR, RTS B 14 5 9 1 Total: 69 TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP Block data transfer EEPMOV Notes: B-byte; W-word; L-longword. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,@-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Rev. 1.00 Jan. 29, 2008 Page 31 of 666 REJ09B0427-0100 Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Symbol Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / Operation Notation Description General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length :8/:16/:24/:32 Rev. 1.00 Jan. 29, 2008 Page 32 of 666 REJ09B0427-0100 Section 2 CPU Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Table 2.3 Instruction MOV Data Transfer Instructions Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in this LSI. Cannot be used in this LSI. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. MOVFPE MOVTPE POP B B W/L PUSH W/L LDM STM Note: * L L Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Jan. 29, 2008 Page 33 of 666 REJ09B0427-0100 Section 2 CPU Table 2.4 Instruction ADD SUB Arithmetic Operations Instructions (1) Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU B B/W/L L B B/W MULXS B/W DIVXU B/W Note: * Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Jan. 29, 2008 Page 34 of 666 REJ09B0427-0100 Section 2 CPU Table 2.4 Instruction DIVXS Arithmetic Operations Instructions (2) Size* B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS*2 MAC B CLRMAC LDMAC STMAC Note: * L Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Jan. 29, 2008 Page 35 of 666 REJ09B0427-0100 Section 2 CPU Table 2.5 Instruction AND Logic Operations Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. OR B/W/L XOR B/W/L NOT B/W/L (Rd) (Rd) Takes the one's complement (logical complement) of general register contents. Note: * Refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Shift Instructions Size* B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shifts are possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shifts are possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotations are possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotations are possible. B/W/L B/W/L B/W/L Refers to the operand size. B: Byte W: Word L: Longword Rev. 1.00 Jan. 29, 2008 Page 36 of 666 REJ09B0427-0100 Section 2 CPU Table 2.7 Instruction BSET Bit Manipulation Instructions (1) Size* B Function 1 ( BCLR B BNOT B ( Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BTST B ( Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BAND B C ( BIAND B BOR B BIOR B Note: * Refers to the operand size. B: Byte Rev. 1.00 Jan. 29, 2008 Page 37 of 666 REJ09B0427-0100 Section 2 CPU Table 2.7 Instruction BXOR Bit Manipulation Instructions (2) Size*1 B Function C ( BIXOR B BLD B BILD B ( Transfers the inverse of a specified bit in a general register or memory operand to the carry flag. The bit number is specified by 3-bit immediate data. BST B C ( BIST B C ( Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data. Note: * Refers to the operand size. B: Byte Rev. 1.00 Jan. 29, 2008 Page 38 of 666 REJ09B0427-0100 Section 2 CPU Table 2.8 Instruction Bcc Branch Instructions Size Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1 JMP BSR JSR RTS Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine Rev. 1.00 Jan. 29, 2008 Page 39 of 666 REJ09B0427-0100 Section 2 CPU Table 2.9 Instruction TRAPA RTE SLEEP LDC System Control Instructions Size* B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves general register or memory contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically XORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. STC B/W ANDC ORC XORC NOP Note: * B B B Refers to the operand size. B: Byte W: Word Rev. 1.00 Jan. 29, 2008 Page 40 of 666 REJ09B0427-0100 Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction EEPMOV.B Size Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W Rev. 1.00 Jan. 29, 2008 Page 41 of 666 REJ09B0427-0100 Section 2 CPU 2.6.2 Basic Instruction Formats The H8S/2600 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.11 shows examples of instruction formats. * Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branching condition of Bcc instructions. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA(disp) rn rm MOV.B @(d:16, Rn), Rm, etc. (4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) Rev. 1.00 Jan. 29, 2008 Page 42 of 666 REJ09B0427-0100 Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 2.7.1 Register DirectRn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). Rev. 1.00 Jan. 29, 2008 Page 43 of 666 REJ09B0427-0100 Section 2 CPU 2.7.3 Register Indirect with Displacement@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.4 Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn Register indirect with post-increment@ERn+: The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. Register indirect with pre-decrement@-ERn: The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For the word or longword transfer instructions, the register value should be even. 2.7.5 Absolute Address@aa:8, @aa:16, @aa:24, or @aa:32 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). Table 2.12 indicates the accessible absolute address ranges. To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Rev. 1.00 Jan. 29, 2008 Page 44 of 666 REJ09B0427-0100 Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) Normal Mode* H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Note: Normal mode is not available in this LSI. 2.7.6 Immediate#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.7 Program-Counter Relative@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 2.7.8 Memory Indirect@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Rev. 1.00 Jan. 29, 2008 Page 45 of 666 REJ09B0427-0100 Section 2 CPU Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) Note: Normal mode is not available in this LSI. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode* Note: * Normal mode is not available in this LSI. (a) Advanced Mode Figure 2.12 Branch Address Specification in Memory Indirect Mode 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Rev. 1.00 Jan. 29, 2008 Page 46 of 666 REJ09B0427-0100 Section 2 CPU Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format Register direct(Rn) Effective Address Calculation Effective Address (EA) Operand is general register contents. op 2 rm rn 31 General register contents Register indirect(@ERn) 0 31 24 23 0 Don't care op 3 r Register indirect with displacement @(d:16,ERn) or @(d:32,ERn) 31 General register contents 0 31 24 23 0 op r disp 31 Sign extension Don't care 0 disp 4 Register indirect with post-increment or pre-decrement *Register indirect with post-increment @ERn+ 31 General register contents 0 31 24 23 0 Don't care op r 31 1, 2, or 4 *Register indirect with pre-decrement @-ERn 0 General register contents 31 24 23 0 Don't care op r Operand Size Byte Word Longword 1, 2, or 4 Offset 1 2 4 Rev. 1.00 Jan. 29, 2008 Page 47 of 666 REJ09B0427-0100 Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Absolute address Effective Address Calculation Effective Address (EA) @aa:8 op abs 31 24 23 H'FFFF 87 0 Don't care @aa:16 op abs 31 24 23 16 15 0 Don't care Sign extension @aa:24 op abs 31 24 23 0 Don't care @aa:32 op abs 31 24 23 0 Don't care 6 Immediate #xx:8/#xx:16/#xx:32 op IMM Operand is immediate data. 7 Program-counter relative @(d:8,PC)/@(d:16,PC) 23 PC contents 0 op disp 23 Sign extension 0 disp 31 24 23 0 Don't care 8 Memory indirect @@aa:8 * Normal mode* 31 op abs H'000000 15 87 abs 0 0 Memory contents 31 24 23 16 15 H'00 0 Don't care * Advanced mode 31 op abs 31 Memory contents 87 H'000000 abs 0 31 24 23 Don't care 0 0 Note: * Normal mode is not available in this LSI. Rev. 1.00 Jan. 29, 2008 Page 48 of 666 REJ09B0427-0100 Section 2 CPU 2.8 Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.13 indicates the state transitions. * Reset State In this state, the CPU and all on-chip peripheral modules are initialized and not operating. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, refer to section 4, Exception Handling. The reset state can also be entered by a watchdog timer overflow. * Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source, such as a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. For further details, refer to section 4, Exception Handling. * Program Execution State In this state, the CPU executes program instructions in sequence. * Bus-Released State The bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further details, refer to section 21, Power-Down Modes. Rev. 1.00 Jan. 29, 2008 Page 49 of 666 REJ09B0427-0100 Section 2 CPU End of bus request Bus request Program execution state End of bus request Bus request SLEEP instruction with SSBY = 1 SLEEP instruction with SSBY = 0 Bus-released state End of exception handling Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt request RES = high Software standby mode Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. 3. For details, refer to section 21, Power-Down Modes. Figure 2.13 State Transitions Rev. 1.00 Jan. 29, 2008 Page 50 of 666 REJ09B0427-0100 Section 2 CPU 2.9 2.9.1 Usage Note Notes on Using the Bit Operation Instruction Instructions BSET, BCLR, BNOT, BST, and BIST read data in byte units, and write data in byte units after bit operation. Therefore, attention must be paid when these instructions are used for ports or registers including write-only bits. Instruction BCLR can be used to clear the flag in the internal I/O register to 0. If it is obvious that the flag has been set to 1 by the interrupt processing routine, it is unnecessary to read the flag beforehand. Rev. 1.00 Jan. 29, 2008 Page 51 of 666 REJ09B0427-0100 Section 2 CPU Rev. 1.00 Jan. 29, 2008 Page 52 of 666 REJ09B0427-0100 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports four operating modes (modes 4 to 7). These modes are determined by the mode pin (MD2 to MD0) setting. Do not change the mode pin settings during operation. Table 3.1 MCU Operating Mode Selection CPU Operating Mode Advanced mode Advanced mode Advanced mode Advanced mode On-Chip ROM Disabled Disabled Enabled Enabled MCU Operating Mode MD2 4 5 6 7 1 1 1 1 MD1 0 0 1 1 MD0 0 1 0 1 Description Expanded mode with on-chip ROM disabled Expanded mode with on-chip ROM disabled Expanded mode with on-chip ROM enabled Single-chip mode Rev. 1.00 Jan. 29, 2008 Page 53 of 666 REJ09B0427-0100 Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode. * Mode control register (MDCR) * System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) Initial Value 1 All 0 Bit 7 6 to 3 Bit Name R/W Descriptions Reserved This bit is always read as 1 and cannot be modified. Reserved These bits are always read as 0 and cannot be modified. 2 1 0 MDS2 MDS1 MDS0 * * * R R R Mode select 2 to 0 These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are readonly bits and they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a reset. These latches are canceled by a power-on reset. Note: * Determined by pins MD2 to MD0. Rev. 1.00 Jan. 29, 2008 Page 54 of 666 REJ09B0427-0100 Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) SYSCR selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and enables or disables on-chip RAM. Bit 7 Bit Name MACS Initial Value 0 R/W R/W Descriptions MAC Saturation Selects either saturating or non-saturating calculation for the MAC instruction. 0: Non-saturating calculation for the MAC instruction 1: Saturating calculation for the MAC instruction 6 5 4 INTM1 INTM0 0 0 0 R/W R/W Reserved This bit is always read as 0 and cannot be modified. These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.6, Interrupt Control Modes and Interrupt Operation. 00: Interrupt control mode 0 01: Setting prohibited 10: Interrupt control mode 2 11: Setting prohibited 3 NMIEG 0 R/W NMI Edge Select Selects the valid edge of the NMI interrupt input. 0: An interrupt is requested at the falling edge of NMI input 1: An interrupt is requested at the rising edge of NMI input 2, 1 All 0 Reserved These bits are always read as 0 and cannot be modified. 0 RAME 1 R/W RAM Enable Enables or disables on-chip RAM. The RAME bit is initialized when the reset status is released. 0: On-chip RAM is disabled 1: On-chip RAM is enabled Rev. 1.00 Jan. 29, 2008 Page 55 of 666 REJ09B0427-0100 Section 3 MCU Operating Modes 3.3 3.3.1 Operating Mode Descriptions Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports 1, A, B, and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The bus mode immediately after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.2 Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports1, A, B, and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. The bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16-bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.3 Mode 6 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports 1, A, B, and C function as input port pins immediately after a reset. Address output can be performed by setting the corresponding DDR (data direction register) bits to 1. Port D functions as a data bus, and part of port F carries bus control signals. The bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16-bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.4 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input/output ports. Rev. 1.00 Jan. 29, 2008 Page 56 of 666 REJ09B0427-0100 Section 3 MCU Operating Modes 3.4 Pin Functions in Each Operating Mode The pin functions of ports A to F vary depending on the operating mode. Table 3.2 shows their functions in each operating mode. Table 3.2 Port Port 1 P11 to P13 P10 Port A Port B Port C Port D Port E Port F PF7 PF6 to PF4 PF3 PF0 [Legend] P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *: After reset Pin Functions in Each Mode Mode 4 P*/A P/A* P/A* P/A* A D P/D* P/C* C P/C* P*/C Mode 5 P*/A P/A* P/A* P/A* A D P*/D P/C* C P*/C P*/C Mode 6 P*/A P*/A P*/A P*/A P*/A D P*/D P/C* C P*/C P*/C Mode 7 P P P P P P P P*/C P Rev. 1.00 Jan. 29, 2008 Page 57 of 666 REJ09B0427-0100 Section 3 MCU Operating Modes 3.5 Address Map Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 External address space On-chip ROM On-chip ROM H'03FFFF H'FFAFFF H'FFB000 H'FFDFFF H'FFE000 Reserved area On-chip RAM * H'FFEFC0 H'FFF800 Internal I/O registers H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF Note: External area Internal I/O registers On-chip RAM * H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF External address space H'03FFFF External address space Reserved area H'FFE000 On-chip RAM * H'FFEFBF On-chip RAM H'FFAFFF H'FFB000 H'FFDFFF H'FFE000 H'FFEFC0 H'FFF800 External address space H'FFF800 Internal I/O registers H'FFFF3F External area Internal I/O registers On-chip RAM * H'FFFF60 H'FFFFC0 H'FFFFFF Internal I/O registers On-chip RAM Internal I/O registers * External address can be accessed by clearing th RAME bit in SYSCR to 0. Figure 3.1 Address Map (H8S/2605) Rev. 1.00 Jan. 29, 2008 Page 58 of 666 REJ09B0427-0100 Section 3 MCU Operating Modes Mode 4, 5 (advanced expanded mode with on-chip ROM disabled) Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 H'000000 On-chip RAM (Mask ROM version) On-chip RAM (Mask ROM version) H'01FFFF External address space H'01FFFF Reserved area H'03FFFF H'FFAFFF H'FFB000 On-chip RAM * H'FFAFFF H'FFB000 External address space H'FFB000 On-chip RAM * H'FFEFBF On-chip RAM H'FFEFC0 H'FFF800 External address space H'FFEFC0 H'FFF800 External address space H'FFF800 Internal I/O registers Internal I/O registers H'FFFF3F External area Internal I/O registers On-chip RAM * H'FFFF60 H'FFFFC0 H'FFFFFF Internal I/O registers On-chip RAM Internal I/O registers H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF Note: External area Internal I/O registers On-chip RAM * H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF * External address can be accessed by clearing th RAME bit in SYSCR to 0. Figure 3.2 Address Map (H8S/2606) Rev. 1.00 Jan. 29, 2008 Page 59 of 666 REJ09B0427-0100 Section 3 MCU Operating Modes Mode 4, 5 (advanced expanded mode with on-chip ROM disabled) Mode 6 (advanced expanded mode with on-chip ROM enabled) Mode 7 (advanced single-chip mode) H'000000 H'000000 H'000000 On-chip RAM (F-ZTAT/ Mask ROM version) On-chip RAM (F-ZTAT/ Mask ROM version) External address space H'01FFFF H'01FFFF Reserved area H'03FFFF H'FFAFFF H'FFB000 On-chip RAM * H'FFAFFF H'FFB000 External address space H'FFB000 On-chip RAM H'FFEFBF On-chip RAM * H'FFEFC0 H'FFF800 External address space H'FFEFC0 H'FFF800 External address space H'FFF800 Internal I/O registers Internal I/O registers H'FFFF3F External area Internal I/O registers On-chip RAM * H'FFFF60 H'FFFFC0 H'FFFFFF Internal I/O registers On-chip RAM Internal I/O registers H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF Note: External area Internal I/O registers On-chip RAM * H'FFFF40 H'FFFF60 H'FFFFC0 H'FFFFFF * External address can be accessed by clearing th RAME bit in SYSCR to 0. Figure 3.3 Address Map (H8S/2607) Rev. 1.00 Jan. 29, 2008 Page 60 of 666 REJ09B0427-0100 Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As shown in table 4.1, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, refer to section 5, Interrupt Controller. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit in EXR is set to 1. Starts when a direction transition occurs as the result of SLEEP instruction execution. Starts when execution of the current instruction or exception 2 handling ends, if an interrupt request has been issued.* Started by execution of a trap instruction (TRAPA). Trace*1 Direct transition Interrupt Low Trap instruction *3 Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state. Rev. 1.00 Jan. 29, 2008 Page 61 of 666 REJ09B0427-0100 Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for details on each product, refer to section 3, MCU Operating Modes. Table 4.2 Exception Handling Vector Table Vector Address*1 Exception Source Power-on reset Reserved for system use Vector Number 0 1 2 3 4 Trace 4 Normal Mode*2 H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0019 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F 5 Interrupt (direct transitions)* 6 Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) Reserved for system use 7 8 9 10 11 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved for system use 16 17 18 19 20 21 22 23 Rev. 1.00 Jan. 29, 2008 Page 62 of 666 REJ09B0427-0100 Section 4 Exception Handling Vector Address*1 Exception Source Internal interrupt* 3 Vector Number 24 127 Normal Mode*2 H'0030 to H'0031 H'00FE to H'00FF Advanced Mode H'0060 to H'0063 H'01FC to H'01FF Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling Vector Table. 4. For direct transitions, see section 21.10, Direct Transitions. 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer. For details, see section 12, Watchdog Timer (WDT). The interrupt control mode is 0 immediately after reset. 4.3.1 Reset Exception Handling When the RES pin goes high after being held low for the necessary period, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, the T bit in EXR is cleared to 0, and the I bit in EXR and CCR is set to 1. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4.1 and 4.2 show examples of the reset sequence. Rev. 1.00 Jan. 29, 2008 Page 63 of 666 REJ09B0427-0100 Section 4 Exception Handling Vector fetch Fetch of first Internal processing program instruction RES Internal address bus (1) (3) (5) Internal read signal Internal write signal Internal data bus High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled) Rev. 1.00 Jan. 29, 2008 Page 64 of 666 REJ09B0427-0100 Section 4 Exception Handling Vector fetch Internal processing Fetch of first program instruction * * * RES Address bus (1) (3) (5) RD HWR, LWR High D15 to D0 (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note:* Three program wait states are inserted. Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled) Rev. 1.00 Jan. 29, 2008 Page 65 of 666 REJ09B0427-0100 Section 4 Exception Handling 4.3.2 Interrupts after Reset If an interrupt is accepted immediately after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset exception handling is executed. Since the first instruction of a program is always executed immediately after the reset, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.3 State of On-Chip Peripheral Modules after Reset Release After reset release, MSTPCRA to MSTPCRA are initialized to H'3F, H'FF, and H'FF, and B'11xxxxxx respectively, and all modules except the DTC enter module stop mode. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when the module stop mode is cancelled. Note: The initial values of bits 5 to 0 in MSTPCRD are undefined. 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt mask bit in CCR. Table 4.3 shows the states of CCR and EXR after execution of trace exception handling. Trace mode is cancelled by clearing the T bit in EXR to 0 with the trace exception handling. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Rev. 1.00 Jan. 29, 2008 Page 66 of 666 REJ09B0427-0100 Section 4 Exception Handling Table 4.3 Statuses of CCR and EXR after Trace Exception Handling CCR EXR I2 to I0 T Interrupt Control Mode 0 2 I UI Trace exception handling cannot be used. 1 -- -- 0 [Legend] 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution 4.5 Interrupts Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR) are saved to the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution begins from that address. Rev. 1.00 Jan. 29, 2008 Page 67 of 666 REJ09B0427-0100 Section 4 Exception Handling 4.6 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended control register (EXR) are saved to the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the statuses of CCR and EXR after execution of trap instruction exception handling. Table 4.4 Statuses of CCR and EXR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI I2 to I0 EXR T 0 [Legend] 1: Set to 1 0: Cleared to 0 : Retains value prior to execution Rev. 1.00 Jan. 29, 2008 Page 68 of 666 REJ09B0427-0100 Section 4 Exception Handling 4.7 Stack Status after Exception Handling Figures 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes*2 SP EXR Reserved*1 SP CCR CCR*1 PC (16 bits) CCR CCR*1 PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes SP EXR Reserved*1 SP CCR PC (24 bits) CCR PC (24 bits) Interrupt control mode 0 Notes: 1. Ignored on return. 2. Normal modes are not available in this LSI. Interrupt control mode 2 Figure 4.3 Stack Status after Exception Handling Rev. 1.00 Jan. 29, 2008 Page 69 of 666 REJ09B0427-0100 Section 4 Exception Handling 4.8 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of what happens when the SP value is odd. Address CCR SP PC SP R1L H'FFFEFA H'FFFEFB PC H'FFFEFC H'FFFEFD H'FFFEFE SP H'FFFEFF SP set to H'FFFEFF TRAP instruction executed Data saved above SP MOV.B R1L, @-ER7 instruction executed Contents of CCR lost [Legend] CCR : PC : R1L : SP : Condition code register Program counter General register R1L Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4.4 Operation when SP Value Is Odd Rev. 1.00 Jan. 29, 2008 Page 70 of 666 REJ09B0427-0100 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features * Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Seven external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ5 to IRQ0. * DTC control The DTC can be activated by an interrupt request. Rev. 1.00 Jan. 29, 2008 Page 71 of 666 REJ09B0427-0100 Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I Interrupt request Vector number CPU Internal interrupt request SWDTEND to CMI.2 CCR I2 to I0 EXR IPR Interrupt controller [Legend] ISCR: IER: ISR: IPR: SYSCR: IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register Figure 5.1 Block Diagram of Interrupt Controller Rev. 1.00 Jan. 29, 2008 Page 72 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Name NMI IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Pin Configuration I/O Input Input Input Input Input Input Input Function Nonmaskable external interrupt Rising or falling edge can be selected Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected Rev. 1.00 Jan. 29, 2008 Page 73 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.3 Register Descriptions The interrupt controller has the following registers. For the system control register (SYSCR), refer to section 3.2.2, System Control Register (SYSCR). * * * * * * * * * * * * * * * * * System control register (SYSCR) IRQ sense control register H (ISCRH) IRQ sense control register L (ISCRL) IRQ enable register (IER) IRQ status register (ISR) Interrupt priority register A (IPRA) Interrupt priority register B (IPRB) Interrupt priority register C (IPRC) Interrupt priority register D (IPRD) Interrupt priority register E (IPRE) Interrupt priority register F (IPRF) Interrupt priority register G (IPRG) Interrupt priority register H (IPRH) Interrupt priority register J (IPRJ) Interrupt priority register K (IPRK) Interrupt priority register L (IPRL) Interrupt priority register M (IPRM) Rev. 1.00 Jan. 29, 2008 Page 74 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.3.1 Interrupt Priority Registers A to H, J, K, L, and M (IPRA to IPRH, IPRJ, IPRK, IPRL, and IPRM) The IPR registers set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 0 to 2 and 4 to 6 sets the priority of the corresponding interrupt. Bit 7 6 5 4 Bit Name Initial Value 0 1 1 1 R/W Description Reserved These bits are always read as 0. IPR6 IPR5 IPR4 R/W R/W R/W These bits set the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 3 2 1 0 IPR2 IPR1 IPR0 0 1 1 1 R/W R/W R/W Reserved These bits are always read as 0. These bits set the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) Rev. 1.00 Jan. 29, 2008 Page 75 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.3.2 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that controls the enabling and disabling of interrupt requests IRQ0 to IRQ5. Bit 7, 6 5 4 3 2 1 0 Bit Name Initial Value All 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The write value should always be 0. IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1. IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1. Rev. 1.00 Jan. 29, 2008 Page 76 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ0 to IRQ5. * Bit 15 to 12 11 10 ISCRH Initial Bit Name Value R/W R/W R/W R/W Description Reserved The write value should always be 0. IRQ5SCB 0 IRQ5SCA 0 IRQ5 Sense Control B IRQ5 Sense Control A 00: Interrupt request generated at IRQ5 input level low 01: Interrupt request generated at falling edge of IRQ5 input 10: Interrupt request generated at rising edge of IRQ5 input 11: Interrupt request generated at both falling and rising edges of IRQ5 input All 0 9 8 IRQ4SCB 0 IRQ4SCA 0 R/W R/W IRQ4 Sense Control B IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input level low 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input Rev. 1.00 Jan. 29, 2008 Page 77 of 666 REJ09B0427-0100 Section 5 Interrupt Controller * Bit 7 6 ISCRL Initial Bit Name Value IRQ3SCB 0 IRQ3SCA 0 R/W R/W R/W Description IRQ3 Sense Control B IRQ3 Sense Control A 00: Interrupt request generated at IRQ3 input level low 01: Interrupt request generated at falling edge of IRQ3 input 10: Interrupt request generated at rising edge of IRQ3 input 11: Interrupt request generated at both falling and rising edges of IRQ3 input 5 4 IRQ2SCB 0 IRQ2SCA 0 R/W R/W IRQ2 Sense Control B IRQ2 Sense Control A 00: Interrupt request generated at IRQ2 input level low 01: Interrupt request generated at falling edge of IRQ2 input 10: Interrupt request generated at rising edge of IRQ2 input 11: Interrupt request generated at both falling and rising edges of IRQ2 input 3 2 IRQ1SCB 0 IRQ1SCA 0 R/W R/W IRQ1 Sense Control B IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input level low 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input 1 0 IRQ0SCB 0 IRQ0SCA 0 R/W R/W IRQ0 Sense Control B IRQ0 Sense Control A 00: Interrupt request generated at IRQ0 input level low 01: Interrupt request generated at falling edge of IRQ0 input 10: Interrupt request generated at rising edge of IRQ0 input 11: Interrupt request generated at both falling and rising edges of IRQ0 input Rev. 1.00 Jan. 29, 2008 Page 78 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.3.4 IRQ Status Register (ISR) ISR indicates the status of IRQ0 to IRQ5 interrupt requests. Bit 7, 6 5 4 3 2 1 0 Bit Name Initial Value All 0 0 0 0 0 0 0 R/W R/W* R/W* R/W* R/W* R/W* R/W* R/W* Description Reserved These bits are always read as 0. IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F [Setting condition] When the interrupt source selected by the ISCR registers occurs [Clearing conditions] * * * * Note: * Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 Only 0 can be written to clear the flag. Rev. 1.00 Jan. 29, 2008 Page 79 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Sources External Interrupts There are seven external interrupts: NMI and IRQ0 to IRQ5. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. IRQ0 to IRQ5 Interrupts: Interrupts IRQ0 to IRQ5 are requested by an input signal at pins IRQ0 to IRQ5. Interrupts IRQ0 to IRQ5 have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ0 to IRQ5. * Enabling or disabling of interrupt requests IRQ0 to IRQ5 can be selected with IER. * The interrupt priority level can be set with IPR. * The status of interrupt requests IRQ0 to IRQ5 is indicated in ISR. ISR flags can be cleared to 0 by software. The detection of IRQ0 to IRQ5 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0; and use the pin as an I/O pin for another function. A block diagram of interrupts IRQ0 to IRQ5 is shown in figure 5.2. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: n = 5 to 0 S R Q IRQn interrupt request Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5 Rev. 1.00 Jan. 29, 2008 Page 80 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.4.2 Internal Interrupts The sources for internal interrupts from on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. * The interrupt priority level can be set by means of IPR. * The DTC can be activated by a TPU, SCI, or other interrupt request. * When the DTC is activated by an interrupt request, it is not affected by the interrupt control mode or CPU interrupt mask bit. 5.5 Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Rev. 1.00 Jan. 29, 2008 Page 81 of 666 REJ09B0427-0100 Section 5 Interrupt Controller Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Interrupt Source Origin of Interrupt Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Vector Number 7 16 17 18 19 20 21 22 23 24 25 27 28 29 32 33 34 35 36 40 41 42 43 44 45 46 47 Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'006C H'0070 H'0074 H'0080 H'0084 H'0088 H'008C H'0090 H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC IPR IPRA6 to IPRA4 IPRA2 to IPRA0 IPRB6 to IPRB4 IPRB2 to IPRB0 IPRC2 to IPRC0 IPRD6 to IPRD4 IPRE6 to IPRE4 IPRE2 to IPRE0 IPRF6 to IPRF4 Priority High External pin NMI Reserved for system use Reserved for system use DTC WDT_0 PC break control A/D WDT_1 TPU_0 SWDTEND WOVI0 PC break ADI WOVI1 TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 TPU_1 TGIA_1 TGIB_1 TCIV_1 TCIU_1 IPRF2 to IPRF0 TPU_2 TGIA_2 TGIB_2 TCIV_2 TCIU_2 IPRG6 to IPRG4 Low Rev. 1.00 Jan. 29, 2008 Page 82 of 666 REJ09B0427-0100 Section 5 Interrupt Controller Vector Address* Interrupt Source TPU_3 Origin of Interrupt Source TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 TPU_4 TGIA_4 TGIB_4 TCIV_4 TCIU_4 TPU_5 TGIA_5 TGIB_5 TCIV_5 TCIU_5 SCI_0 ERI_0 RXI_0 TXI_0 TEI_0 SCI_1 ERI_1 RXI_1 TXI_1 TEI_1 SCI_2 ERI_2 RXI_2 TXI_2 TEI_2 IIC-0 IIC-1 IIICI0 DDCSW1 IICI1 Reserved for system use Vector Number 48 49 50 51 52 56 57 58 59 60 61 62 63 80 81 82 83 84 85 86 87 88 89 90 91 100 101 102 103 Advanced Mode H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C H'0190 H'0194 H'0198 H'019C Low IPRL2 to IPRLO IPRK2 to IPRK0 IPRK6 to IPRK4 IPRJ2 to IPRJ0 IPRH2 to IPRH0 IPRH6 to IPRH4 IPR IPRG2 to IPRG0 Priority High Rev. 1.00 Jan. 29, 2008 Page 83 of 666 REJ09B0427-0100 Section 5 Interrupt Controller Vector Address* Interrupt Source Origin of Interrupt Source Vector Number 104 Advanced Mode H'01A0 IPR IPRM6 to IPRM4 Priority High Motor CMI_1 control PWM timer CMI_2 Note: * 105 H'01A4 Low Lower 16 bits of the start address. Rev. 1.00 Jan. 29, 2008 Page 84 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by SYSCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.3 Interrupt Control Modes Interrupt Mask Bits Description I The priorities of interrupt sources are fixed at the default settings. Interrupt sources, except for NMI, are masked by the I bit. 8 priority levels other than NMI can be set with IPR. 8-level interrupt mask control is performed by bits I2 to I0. Interrupt Priority Setting Control Mode Registers 0 Default 2 IPR I2 to I0 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests other than for NMI are masked by the I bit in CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. If the I bit in CCR is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. If the I bit is cleared, an interrupt request is accepted. 3. When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels is selected and other interrupt requests are held pending. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. Rev. 1.00 Jan. 29, 2008 Page 85 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution status Interrupt generated? Yes Yes No NMI No I=0 Yes No Hold pending No IRQ0 Yes No IRQ1 Yes CMI_2 Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 1.00 Jan. 29, 2008 Page 86 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is applied to eight levels for interrupt requests other than NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5.2 is selected. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Rev. 1.00 Jan. 29, 2008 Page 87 of 666 REJ09B0427-0100 Section 5 Interrupt Controller Program execution status Interrupt generated? Yes Yes NMI No No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes No Level 1 interrupt? Mask level 5 or below? Yes Mask level 0? Yes No Yes No No Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 Rev. 1.00 Jan. 29, 2008 Page 88 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev. 1.00 Jan. 29, 2008 Page 89 of 666 REJ09B0427-0100 REJ09B0427-0100 Interrupt acceptance Internal operation stack Vector fetch Internal operation Interrupt service routine instruction prefetch (1) (3) (5) (7) (9) (11) (13) (2) (4) (6) (8) (10) (12) (14) (6) (8) (9) (11) (10) (12) (13) (14) Saved PC and saved CCR Vector address Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((13) = (10)(12)) First instruction of interrupt handling routine Section 5 Interrupt Controller Interrupt level determination Instruction Wait for end of instruction prefetch Rev. 1.00 Jan. 29, 2008 Page 90 of 666 Interrupt request signal Internal address bus Internal read signal Internal write signal Figure 5.5 Interrupt Exception Handling Internal data bus (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, has the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.4 Interrupt Response Times Normal Mode*5 Interrupt control mode 0 3 Interrupt control mode 2 3 Advanced Mode Interrupt control mode 0 3 Interrupt control mode 2 3 No. 1 2 3 4 5 6 Execution Status Interrupt priority determination*1 Number of wait states until executing 1 to 19 +2*SI 1 to 19+2*SI instruction ends*2 PC, CCR, EXR stack save Vector fetch Instruction fetch*3 Internal processing* 4 1 to 19+2*SI 1 to 19+2*SI 2*SK 2*SI 2*SI 2 12 to 32 3*SK 2*SI 2*SI 2 13 to 33 2*SK SI 2*SI 2 11 to 31 3*SK SI 2*SI 2 12 to 32 Total (using on-chip memory) Notes: 1. 2. 3. 4. 5. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Not available in this LSI. Rev. 1.00 Jan. 29, 2008 Page 91 of 666 REJ09B0427-0100 Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Status Object of Access External Device 8-Bit Bus 16-Bit Bus 2-State Access 2 3-State Access 3+m Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6+2m [Legend] m: Number of wait states in an external device access. 5.6.5 DTC Activation by Interrupt The DTC can be activated by an interrupt. For details, see section 8, Data Transfer Controller (DTC). Rev. 1.00 Jan. 29, 2008 Page 92 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.7 5.7.1 Usage Notes Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 5.6 shows an example in which the TCIEV bit in TIER_0 of the TPU is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. TIER_0 write cycle by CPU TCIVexception handling Internal address bus TIER_0 address Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.6 Conflict between Interrupt Generation and Disabling Rev. 1.00 Jan. 29, 2008 Page 93 of 666 REJ09B0427-0100 Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.3 When Interrupts Are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.7.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 Rev. 1.00 Jan. 29, 2008 Page 94 of 666 REJ09B0427-0100 Section 6 PC Break Controller (PBC) Section 6 PC Break Controller (PBC) The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. A block diagram of the PC break controller is shown in figure 6.1. 6.1 Features * Two break channels (A and B) * 24-bit break address Bit masking possible * Four types of break compare conditions Instruction fetch data read data write data read/write * Bus master Either CPU or CPU/DTC can be selected * The timing of PC break exception handling after the occurrence of a break condition is as follows: Immediately before execution of the instruction fetched at the set address (instruction fetch) Immediately after execution of the instruction that accesses data at the set address (data access) * Module stop mode can be set Rev. 1.00 Jan. 29, 2008 Page 95 of 666 REJ09B0427-0100 Section 6 PC Break Controller (PBC) BARA BCRA Output control Mask control Comparator Internal address Control logic Access status PC break interrupt Comparator Match signal Control logic Output control Mask control BARB BCRB Figure 6.1 Block Diagram of PC Break Controller 6.2 Register Descriptions The PC break controller has the following registers. * * * * Break address register A (BARA) Break address register B (BARB) Break control register A (BCRA) Break control register B (BCRB) Break Address Register A (BARA) 6.2.1 BARA is a 32-bit readable/writable register that specifies the channel A break address. Bit 31 to 24 Bit Name Initial Value R/W Description Reserved These bits are read as an undefined value and cannot be modified. 23 to 0 BAA23 to BAA0 H'000000 R/W These bits set the channel A PC break address. Undefined Rev. 1.00 Jan. 29, 2008 Page 96 of 666 REJ09B0427-0100 Section 6 PC Break Controller (PBC) 6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) BCRA controls channel A PC breaks. BCRA also contains a condition match flag. Bit 7 Bit Name CMFA Initial Value 0 R/W R/W Description Condition Match Flag A [Setting condition] When a condition set for channel A is satisfied [Clearing condition] When 0 is written to CMFA after reading CMFA = 1 6 CDA 0 R/W CPU Cycle/DTC Cycle Select A Selects the channel A break condition bus master. 0: CPU 1: CPU or DTC 5 4 3 BAMRA2 BAMRA1 BAMRA0 0 0 0 R/W R/W R/W Break Address Mask Register A2 to A0 These bits specify which bits of the break address set in BARA are to be masked. 000: BAA23 to BAA0 (All bits are unmasked) 001: BAA23 to BAA1 (Lowest bit is masked) 010: BAA23 to BAA2 (Lower 2 bits are masked) 011: BAA23 to BAA3 (Lower 3 bits are masked) 100: BAA23 to BAA4 (Lower 4 bits are masked) 101: BAA23 to BAA8 (Lower 8 bits are masked) 110: BAA23 to BAA12 (Lower 12 bits are masked) 111: BAA23 to BAA16 (Lower 16 bits are masked) Rev. 1.00 Jan. 29, 2008 Page 97 of 666 REJ09B0427-0100 Section 6 PC Break Controller (PBC) Bit 2 1 Bit Name CSELA1 CSELA0 Initial Value 0 0 R/W R/W R/W Description Break Condition Select A Selects break condition of channel A. 00: Instruction fetch is used as break condition 01: Data read cycle is used as break condition 10: Data write cycle is used as break condition 11: Data read/write cycle is used as break condition 0 BIEA 0 R/W Break Interrupt Enable A When this bit is 1, the PC break interrupt request of channel A is enabled. 6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.3 Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt Due to Data Access, taking the example of channel A. 6.3.1 PC Break Interrupt Due to Instruction Fetch 1. Set the break address in BARA. For a PC break caused by an instruction fetch, set the address of the first instruction byte as the break address. 2. Set the break conditions in BCR. Set bit 6 (CDA) to 0 to select the CPU because the bus master must be the CPU for a PC break caused by an instruction fetch. Set the address bits to be masked to bits 3 to 5 (BAMA0 to BAMA2). Set bits 1 and 2 (CSELA0 and CSELA1) to 00 to specify an instruction fetch as the break condition. Set bit 0 (BIEA) to 1 to enable break interrupts. 3. When the instruction at the set address is fetched, a PC break request is generated immediately before execution of the fetched instruction, and the condition match flag (CMFA) is set. 4. After priority determination by the interrupt controller, PC break interrupt exception handling is started. Rev. 1.00 Jan. 29, 2008 Page 98 of 666 REJ09B0427-0100 Section 6 PC Break Controller (PBC) 6.3.2 PC Break Interrupt Due to Data Access 1. Set the break address in BARA. For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address space address as the break address. Stack operations and branch address reads are included in data accesses. 2. Set the break conditions in BCRA. Select the bus master with bit 6 (CDA). Set the address bits to be masked to bits 3 to 5 (BAMA BAMA0 to BAMA2). Set bits 1 and 2 (CSELA0 and CSELA1) to 01, 10, or 11 to specify data access as the break condition. Set bit 0 (BIEA) to 1 to enable break interrupts. 3. After execution of the instruction that performs a data access on the set address, a PC break request is generated and the condition match flag (CMFA) is set. 4. After priority determination by the interrupt controller, PC break interrupt exception handling is started. 6.3.3 PC Break Operation at Consecutive Data Transfer * When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction PC break exception handling is executed after all data transfers have been completed and the EEPMOV.B instruction has ended. * When a PC break interrupt is generated at a DTC transfer address PC break exception handling is executed after the DTC has completed the specified number of data transfers, or after data for which the DISEL bit is set to 1 has been transferred. 6.3.4 Operation in Transitions to Power-Down Modes The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below. 1. When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to sleep mode, or from subactive mode to subsleep mode: After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep mode, and PC break interrupt handling is executed. After execution of PC break interrupt handling, the instruction at the address after the SLEEP instruction is executed (figure 6-2 (A)). 2. When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to subactive mode: Rev. 1.00 Jan. 29, 2008 Page 99 of 666 REJ09B0427-0100 Section 6 PC Break Controller (PBC) After execution of the SLEEP instruction, a transition is made to subactive mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (B)). 3. When the SLEEP instruction causes a transition from subactive mode to high-speed (mediumspeed) mode: After execution of the SLEEP instruction, and following the clock oscillation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6.2 (C)). 4. When the SLEEP instruction causes a transition to software standby mode or watch mode: After execution of the SLEEP instruction, a transition is made to the respective mode, and PC break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6.2 (D)). SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution SLEEP instruction execution PC break exception handling System clock subclock Subclock system clock, oscillation settling time Transition to respective mode (D) Execution of instruction after sleep instruction (A) Direct transition exception handling Subactive mode Direct transition exception handling High-speed (medium-speed) mode PC break exception handling PC break exception handling Execution of instruction after sleep instruction (B) Execution of instruction after sleep instruction (C) Figure 6.2 Operations in Power-Down Mode Transitions Rev. 1.00 Jan. 29, 2008 Page 100 of 666 REJ09B0427-0100 Section 6 PC Break Controller (PBC) 6.3.5 When Instruction Execution Is Delayed by One State While the break interrupt enable bit is set to 1, instruction execution is one state later than usual. * For 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, and RTS) in on-chip ROM or RAM. * When break interrupt by instruction fetch is set, the set address indicates on-chip ROM or RAM space, and that address is used for data access, the instruction will be one state later than in normal operation. * When break interrupt by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip ROM or RAM, the instruction will be one state later than in normal operation. Addressing modes: @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC), @(d:16,PC), @@aa:8 * When break interrupt by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction is NOP or SLEEP, or has #xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the instruction will be one state later than in normal operation. Rev. 1.00 Jan. 29, 2008 Page 101 of 666 REJ09B0427-0100 Section 6 PC Break Controller (PBC) 6.4 6.4.1 Usage Notes Module Stop Mode Setting PBC operation can be disabled or enabled using the module stop control register. The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 21, Power-Down Modes. 6.4.2 PC Break Interrupts The PC break interrupt is shared by channels A and B. The channel from which the request was issued must be determined by the interrupt handler. 6.4.3 CMFA and CMFB The CMFA and CMFB flags are not automatically cleared to 0, so 0 must be written to CMFA or CMFB after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be requested after interrupt handling ends. 6.4.4 PC Break Interrupt when DTC Is Bus Master A PC break interrupt generated when the DTC is the bus master is accepted after the bus mastership has been transferred to the CPU by the bus controller. 6.4.5 PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP, TRAPA, RTE, or RTS Instruction Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the instruction fetch at the next address. 6.4.6 I Bit Set by LDC, ANDC, ORC, or XORC Instruction When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt becomes valid two states after the end of the instruction execution. If a PC break interrupt is set for the instruction following one of these instructions, since interrupts, including NMI, are disabled for a 3-state period in the case of LDC, ANDC, ORC, and XOR, the next instruction is always executed. For details, see section 5, Interrupt Controller. Rev. 1.00 Jan. 29, 2008 Page 102 of 666 REJ09B0427-0100 Section 6 PC Break Controller (PBC) 6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction A PC break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, and is not generated if the instruction at the next address is not executed. 6.4.8 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc Instruction A PC break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, and is not generated if the instruction at the branch destination is not executed. Rev. 1.00 Jan. 29, 2008 Page 103 of 666 REJ09B0427-0100 Section 6 PC Break Controller (PBC) Rev. 1.00 Jan. 29, 2008 Page 104 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Section 7 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the bus masterships--the CPU and data transfer controller (DTC). 7.1 Features * Manages external address space in area units Manages the external address space divided into eight areas of 2 Mbytes Bus specifications can be set independently for each area Burst ROM interface can be set * Basic bus interface 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area * Burst ROM interface Burst ROM interface can be set for area 0 Choice of 1- or 2-state burst access * Idle cycle insertion An idle cycle can be inserted between external read cycles for different areas An idle cycle can be inserted before an external write cycle immediately after an external read cycle * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC Rev. 1.00 Jan. 29, 2008 Page 105 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) A block diagram of the bus controller is shown in figure 7.1. Area decoder Internal address bus ABWCR External bus control signals ASTCR BCRH BCRL Bus controller Internal data bus Internal control signals Bus mode signal Wait controller WCRH WCRL CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal DTC bus acknowledge signal [Legend] ABWCR: ASTCR: BCRH: BCRL: WCRH: WCRL: Bus width control register Access state control register Bus control register H Bus control register L Wait control register H Wait control register L Figure 7.1 Block Diagram of Bus Controller Rev. 1.00 Jan. 29, 2008 Page 106 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.2 Input/Output Pins Table 7.1 summarizes the pin configuration of the bus controller. Table 7.1 Name Address strobe Pin Configuration Symbol AS I/O Output Function Strobe signal indicating that an external address space is accessed and address output on address bus is enabled. Strobe signal indicating that an external address space is being read. Strobe signal indicating that an external address space is written to, and upper half (D15 to D8) of data bus is enabled. Strobe signal indicating that an external address space is written to, and lower half (D7 to D0) of data bus is enabled. Read High write RD HWR Output Output Low write LWR Output 7.3 Register Descriptions The bus controller has the following registers. * * * * * * * Bus width control register (ABWCR) Access state control register (ASTCR) Wait control register H (WTCRH) Wait control register L (WTCRL) Bus control register H (BCRH) Bus control register L (BCRL) Pin function control register (PFCR) Rev. 1.00 Jan. 29, 2008 Page 107 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit 7 6 5 4 3 2 1 0 Note Bit Name ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Initial Value 1/0* 1/0* 1/0* 1/0* 1/0* 1/0* 1/0* 1/0* R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Area 7 to 0 Bus Width Control These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. 0: Area n is designated as 16-bit access space 1: Area n is designated as 8-bit access space (n = 7 to 0) * Initial value is 0 in mode 4, and 1 in modes 5 to 7. 7.3.2 Access State Control Register (ASTCR) ASTCR designates each area in the external address space as either 2-state access space or 3-state access space. Bit 7 6 5 4 3 2 1 0 Bit Name AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Area 7 to 0 Access State Control These bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. Wait state insertion is enabled or disabled at the same time. 0: Area n is designated as 2-state access space Wait state insertion in area n access is disabled 1: Area n is designated as 3-state access space Wait state insertion in area n access is enabled (n = 7 to 0) Rev. 1.00 Jan. 29, 2008 Page 108 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.3.3 Wait Control Registers H and L (WCRH and WCRL) WCRH and WCRL select the number of program wait states for each area in the external address space. * WCRH Bit 7 6 Bit Name W71 W70 Initial Value 1 1 R/W R/W R/W Description Area 7 Wait Control 1 and 0 These bits select the number of program wait states when accessing area 7 while AST7 bit in ASTCR = 1. 00: Program wait not inserted 01: 1 program wait state inserted 10: 2 program wait states inserted 11: 3 program wait states inserted 5 4 W61 W60 1 1 R/W R/W Area 6 Wait Control 1 and 0 These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1. 00: Program wait not inserted 01: 1 program wait state inserted 10: 2 program wait states inserted 11: 3 program wait states inserted 3 2 W51 W50 1 1 R/W R/W Area 5 Wait Control 1 and 0 These bits select the number of program wait states when accessing area 5 while AST5 bit in ASTCR = 1. 00: Program wait not inserted 01: 1 program wait state inserted 10: 2 program wait states inserted 11: 3 program wait states inserted 1 0 W41 W40 1 1 R/W R/W Area 4 Wait Control 1 and 0 These bits select the number of program wait states when accessing area 4 while AST4 bit in ASTCR = 1. 00: Program wait not inserted 01: 1 program wait state inserted 10: 2 program wait states inserted 11: 3 program wait states inserted Rev. 1.00 Jan. 29, 2008 Page 109 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) * WCRL Bit 7 6 Bit Name W31 W30 Initial Value 1 1 R/W R/W R/W Description Area 3 Wait Control 1 and 0 These bits select the number of program wait states when accessing area 3 while AST3 bit in ASTCR = 1. 00: Program wait not inserted 01: 1 program wait state inserted 10: 2 program wait states inserted 11: 3 program wait states inserted 5 4 W21 W20 1 1 R/W R/W Area 2 Wait Control 1 and 0 These bits select the number of program wait states when accessing area 2 while AST2 bit in ASTCR = 1. 00: Program wait not inserted 01: 1 program wait state inserted 10: 2 program wait states inserted 11: 3 program wait states inserted 3 2 W11 W10 1 1 R/W R/W Area 1 Wait Control 1 and 0 These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1. 00: Program wait not inserted 01: 1 program wait state inserted 10: 2 program wait states inserted 11: 3 program wait states inserted 1 0 W01 W00 1 1 R/W R/W Area 0 Wait Control 1 and 0 These bits select the number of program wait states when accessing area 0 while AST0 bit in ASTCR = 1. 00: Program wait not inserted 01: 1 program wait state inserted 10: 2 program wait states inserted 11: 3 program wait states inserted Rev. 1.00 Jan. 29, 2008 Page 110 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.3.4 Bus Control Register H (BCRH) BCRH enables or disables idle cycle insertion and specifies the burst ROM interface. Bit 7 Bit Name ICIS1 Initial Value 1 R/W R/W Description Idle Cycle Insert 1 When consecutive external read cycles are performed in different areas, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 6 ICIS0 1 R/W Idle Cycle Insert 0 When an external read cycle and an external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 5 BRSTRM 0 R/W Burst ROM Enable Selects whether the burst ROM interface is used for area 0. 0: Basic bus interface for area 0 1: Burst ROM interface for area 0 Burst Cycle Select 1 Selects the number of burst cycles for the burst ROM interface. 0: 1 state for a burst cycle 1: 2 states for a burst cycle Burst Cycle Select 0 Selects the number of words that can be accessed in a burst access with the burst ROM interface. 0: Maximum four words in burst access 1: Maximum eight words in burst access 2 to 0 -- All 0 R/W Reserved The write value should always be 0. 4 BRSTS1 1 R/W 3 BRSTS0 0 R/W Rev. 1.00 Jan. 29, 2008 Page 111 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.3.5 Bus Control Register L (BCRL) BCRL selects the write data buffer function and enables or disables input to the WAIT pin. Bit 7 6 5 4 3 2 1 Bit Name WDBE Initial Value 0 0 0 0 1 0 0 R/W R/W R/W R/W R/W R/W R/W Description Reserved The write value should always be 0. Reserved This bit is always read as 0 and cannot be modified. Reserved The write value should always be 0. Reserved The write value should always be 1. Reserved The write value should always be 0. Write Data Buffer Enable Selects the write data buffer function for an external write cycle. 0: Write data buffer function not used 1: Write data buffer function used 0 0 R/W Reserved This bit is always read as 0 and cannot be modified. Rev. 1.00 Jan. 29, 2008 Page 112 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.3.6 Pin Function Control Register (PFCR) PFCR controls the address output in expanded mode with on-chip ROM enabled. Bit Initial Bit Name Value All 0 0/1* 0/1* 0 0/1* R/W R/W R/W R/W R/W Description Reserved The write value should always be 0. 3 2 1 0 AE3 AE2 AE1 AE0 Address Output Enable 3 to 0 These bits enable or disable address outputs A8 to A23 in expanded mode with on-chip ROM. When a pin is enabled for address output, the address is output regardless of the corresponding DDR setting. For a pin disabled for address output, each becomes an output port when the corresponding DDR bit is set to 1. For pins A7 to A0, each becomes an address output when the corresponding DDR bit is set to 1. 0000: A8 to A23 output disabled 0001: A8 output enabled; A9 to A23 output disabled 0010: A8 and A9 output enabled; A10 to A23 output disabled 0011: A8 to A10 output enabled; A11 to A23 output disabled 0100: A8 to A11 output enabled; A12 to A23 output disabled 0101: A8 to A12 output enabled; A13 to A23 output disabled 0110: A8 to A13 output enabled; A14 to A23 output disabled 0111: A8 to A14 output enabled; A15 to A23 output disabled 1000: A8 to A15 output enabled; A16 to A23 output disabled 1001: A8 to A16 output enabled; A17 to A23 output disabled 1010: A8 to A17 output enabled; A18 to A23 output disabled 1011: A8 to A18 output enabled; A19 to A23 output disabled 1100: A8 to A19 output enabled; A20 to A23 output disabled 1101: A8 to A20 output enabled; A21 to A23 output disabled 1110: A8 to A21 output enabled; A22 and A23 output disabled 1111: A8 to A23 output enabled Note: * In expanded mode with on-chip ROM enabled, bits 3 to 0 are initialized to B'0000. In expanded mode with on-chip ROM disabled, bits 3 to 0 are initialized to B'1101. 7 to 4 Rev. 1.00 Jan. 29, 2008 Page 113 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.4 7.4.1 Bus Control Area Division The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external address space in area units. Figure 7.2 shows an outline of the memory map. H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF Advanced mode Figure 7.2 Area Divisions Rev. 1.00 Jan. 29, 2008 Page 114 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.4.2 Bus Specifications The external address space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode is set; if any area is designated as 16-bit access space, 16-bit bus mode is set. Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access space. When 2-state access space is designated, wait insertion is disabled. When 3-state access space is designated, it is possible to insert program waits by means of the WCRH and WCRL, and external waits by means of the WAIT pin. Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 7.2 shows the bus specifications (bus width, number of access states, and program wait states) for each basic bus interface area. Rev. 1.00 Jan. 29, 2008 Page 115 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Table 7.2 ABWCR ABWn 0 Bus Specifications for Each Area (Basic Bus Interface) ASTCR ASTn 0 1 WCRH, WCRL Wn1 -- 0 Wn0 -- 0 1 1 0 1 Bus Specifications (Basic Bus Interface) Bus Width 16 Access States 2 3 Program Wait States 0 0 1 2 3 8 2 3 0 0 1 2 3 1 0 1 -- 0 -- 0 1 1 (n = 0 to 7) 0 1 7.4.3 Memory Interfaces The memory interfaces in this LSI allow direct connection of ROM, SRAM, and so on. The initial state of each area is 3-state access space with the basic bus interface. The initial bus width is selected according to the operating mode. Area 0: Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the space excluding on-chip ROM is external address space. In expanded mode with on-chip ROM disabled, all of area 0 is external address space. Either basic bus interface or burst ROM interface can be selected for area 0. Areas 1 to 6: In externally expanded mode, areas 1 to 6 are all external address space. Only the basic bus interface can be used for areas 1 to 6. Rev. 1.00 Jan. 29, 2008 Page 116 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In externally expanded mode, the space excluding the on-chip RAM and internal I/O registers is external address space. The on-chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in external address space. Only the basic bus interface can be used for area 7. 7.5 Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 7.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external address space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 7.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Upper data bus D15 Lower data bus D0 D8 D7 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 7.3 Access Sizes and Data Alignment Control (8-Bit Access Space) Rev. 1.00 Jan. 29, 2008 Page 117 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 16-Bit Access Space: Figure 7.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus D15 Lower data bus D0 D8 D7 Byte size Byte size Word size Longword size * Even address * Odd address 1st bus cycle 2nd bus cycle Figure 7.4 Access Sizes and Data Alignment Control (16-bit Access Space) Rev. 1.00 Jan. 29, 2008 Page 118 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.5.2 Valid Strobes Table 7.3 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 7.3 Area 8-bit access space 16-bit access space Data Buses Used and Valid Strobes Access Size Byte Read/ Write Read Write Byte Read Address -- -- Even Odd Write Even Odd Word Read Write -- -- HWR LWR RD HWR, LWR Valid Strobe RD HWR RD Valid Invalid Valid Hi-Z Valid Valid Upper Data Bus Lower Data (D15 to D8) Bus (D7 to D0) Valid Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid Note: Hi-Z: High-impedance state Invalid: Input state; input value is ignored. Rev. 1.00 Jan. 29, 2008 Page 119 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.5.3 Basic Timing 8-Bit, 2-State Access Space: Figure 7.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states cannot be inserted. Bus cycle T1 T2 Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Figure 7.5 Bus Timing for 8-Bit, 2-State Access Space Rev. 1.00 Jan. 29, 2008 Page 120 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 8-Bit, 3-State Access Space: Figure 7.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Figure 7.6 Bus Timing for 8-Bit, 3-State Access Space Rev. 1.00 Jan. 29, 2008 Page 121 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 16-Bit, 2-State Access Space: Figures 7.7 to 7.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be inserted. Bus cycle T1 T2 Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Figure 7.7 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access) Rev. 1.00 Jan. 29, 2008 Page 122 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Bus cycle T1 T2 Address bus AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write High impedance D15 to D8 D7 to D0 Valid Figure 7.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) Rev. 1.00 Jan. 29, 2008 Page 123 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Bus cycle T1 T2 Address bus AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 7.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev. 1.00 Jan. 29, 2008 Page 124 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 16-Bit, 3-State Access Space: Figures 7.10 to 7.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 Valid High impedance D7 to D0 Figure 7.10 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access) Rev. 1.00 Jan. 29, 2008 Page 125 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Bus cycle T1 T2 T3 Address bus AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Figure 7.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) Rev. 1.00 Jan. 29, 2008 Page 126 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Bus cycle T1 T2 T3 Address bus AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Figure 7.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) 7.5.4 Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There is a way of inserting wait states: program wait insertion. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings in WCRH and WCRL. Rev. 1.00 Jan. 29, 2008 Page 127 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Figure 7.13 shows an example of wait state insertion timing. By program wait T1 T2 Tw Tw Tw T3 Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Figure 7.13 Example of Wait State Insertion Timing After a power-on reset: 3-state access and insertion of three program wait states Rev. 1.00 Jan. 29, 2008 Page 128 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.6 Burst ROM Interface In this LSI, external space area 0 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space interface enables ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of bit BSTRM in BCRH. Continuous burst accesses of four or eight words can be performed, according to the setting of the BRSTS0 bit in BCRH. One or two states can be selected for burst access. In burst ROM interface space, burst access covers only CPU read accesses. 7.6.1 Basic Timing The number of access states in the initial cycle (full access) with the burst ROM interface is determined by the AST0 setting in ASTCR. Wait states can be inserted when the AST0 bit is set to 1. One or two states can be selected for the burst cycle according to the BRSTS1 bit setting in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, area 0 is a 16-bit access space regardless of the ABW0 bit setting in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to four words is performed. When the BRSTS0 bit is set to 1, burst access of up to eight words is performed. The basic access timing for burst ROM space is shown in figures 7.14 and 7.15. Rev. 1.00 Jan. 29, 2008 Page 129 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Full access T1 T2 T3 T1 Burst access T2 T1 T2 Address bus Only the lower address changes AS RD Data bus Read data Read data Read data Note: n = 1 and 0 Figure 7.14 Example of Burst ROM Access Timing (AST0 = 1 and BRSTS0 = 1) Rev. 1.00 Jan. 29, 2008 Page 130 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Full access T1 T2 Burst access T1 T1 Address bus Only the lower address changes AS RD Data bus Read data Read data Read data Note: n = 1 and 0 Figure 7.15 Example of Burst ROM Access Timing (AST0 = 0 and BRSTS1 = 0) 7.6.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 7.5.4, Wait Control. Wait states cannot be inserted in a burst cycle. 7.6.3 Write Access When a write access to burst ROM interface space is executed, burst access is interrupted at that point and the write access is executed in line with the basic bus interface settings. Write accesses are not performed in burst mode even though burst ROM space is designated. Rev. 1.00 Jan. 29, 2008 Page 131 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.7 7.7.1 Idle Cycle Operation When this LSI accesses external address space, it can insert a 1-state idle cycle (Ti) between bus cycles in the following two cases: (1) when read accesses in different areas occur consecutively and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle, it is possible, for example, to avoid data collisions between memory with a long output floating time (such as ROM) and high-speed memory, I/O interfaces, and so on. Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the ICIS1 bit is set to 1 in BCRH, an idle cycle is inserted at the start of the second read cycle. Figure 7.16 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Address bus CS* (area A) CS* (area B) RD Data bus Address bus CS* (area A) CS* (area B) RD Data bus Data collision Long output floating time (a) No idle cycle insertion (ICIS1 = 0) Idle cycle (b) Idle cycle insertion (ICIS1 = 1, initial value) Note: * The CS signal is generated outside the LSI. Figure 7.16 Example of Idle Cycle Operation (Consecutive Reads in Different Areas) Rev. 1.00 Jan. 29, 2008 Page 132 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCRH, an idle cycle is inserted at the start of the write cycle. Figure 7.17 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the data read from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Address bus CS* (area A) CS* (area B) RD HWR Data bus Address bus CS* (area A) CS* (area B) RD HWR Data bus Data collision Long output floating time (a) No idle cycle insertion (ICIS0 = 0) Idle cycle (b) Idle cycle insertion (ICIS0 = 1, initial value) Note: * The CS signal is generated outside the LSI. Figure 7.17 Example of Idle Cycle Operation (Write after Read) Rev. 1.00 Jan. 29, 2008 Page 133 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the system's load conditions, the RD signal may lag behind the CS signal (generated outside the LSI). An example is shown in figure 7.18. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. Bus cycle A T1 T2 T3 Bus cycle B T1 T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2 Address bus CS* (area A) CS* (area B) Address bus CS* (area A) CS* (area B) RD RD Overlap period between CS (area B) and RD may occur (a) No idle cycle insertion (ICIS1 = 0) Note: * The CS signal is generated outside the LSI. Idle cycle (b) Idle cycle insertion (ICIS1 = 1, initial value) Figure 7.18 Relationship between Chip Select (CS) and Read (RD) 7.7.2 Pin States in Idle Cycle Table 7.4 shows the pin states in an idle cycle. Table 7.4 Pins A23 to A0 D15 to D0 AS RD HWR, LWR Pin States in Idle Cycle Pin State Contents of following bus cycle High impedance High High High Rev. 1.00 Jan. 29, 2008 Page 134 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.8 Write Data Buffer Function This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables external writes to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit to 1 in BCRL. Figure 7.19 shows an example of the timing when the write data buffer function is used. When this function is used, if an external address space write continues for two states or longer, and there is an internal access next, an external write only is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external address space write rather than waiting until it ends. On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 Internal address bus Internal memory Internal read signal Internal I/O register address A23 to A0 External address External space write HWR, LWR D15 to D0 Figure 7.19 Example of Timing when Write Data Buffer Function is Used Rev. 1.00 Jan. 29, 2008 Page 135 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) 7.9 Bus Arbitration This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration). There are two bus masters--the CPU and DTC--that perform read/write operations when they have the bus mastership. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes the bus mastership and begins its operation. 7.9.1 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes the bus mastership until that signal is canceled. The order of priority of the bus masterships is as follows: (High) DTC > CPU (Low) 7.9.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: * The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the component operations. * With bit manipulation instructions such as BSET and BCRL, the sequence of operations is: data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is not transferred during this read-modify-write cycle, which is executed as a series of bus cycles. * If the CPU is in sleep mode, the bus is transferred immediately. Rev. 1.00 Jan. 29, 2008 Page 136 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 7.10 Bus Controller Operation in Reset In a power-on reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted. Rev. 1.00 Jan. 29, 2008 Page 137 of 666 REJ09B0427-0100 Section 7 Bus Controller (BSC) Rev. 1.00 Jan. 29, 2008 Page 138 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 8.1 shows a block diagram of the DTC. The DTC's register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. 8.1 Features * Transfer is possible over any number of channels * Three transfer modes Normal, repeat, and block transfer modes are available * One activation source can trigger a number of data transfers (chain transfer) * The direct specification of 16-Mbyte address space is possible * Activation by software is possible * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC * Module stop mode can be set Rev. 1.00 Jan. 29, 2008 Page 139 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) Internal address bus On-chip RAM Interrupt controller DTC DTCERA to DTCERG Control logic Interrupt request CPU interrupt request [Legend] MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERG: DTVECR: DTC service request DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC destination address register DTC enable registers A to G DTC vector register Figure 8.1 Block Diagram of DTC Rev. 1.00 Jan. 29, 2008 Page 140 of 666 REJ09B0427-0100 MRA MRB CRA CRB DAR SAR Internal data bus Register information DTVECR Section 8 Data Transfer Controller (DTC) 8.2 Register Descriptions The DTC has the following registers. * * * * * * DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set of register information that is stored in on-chip RAM to the corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated register information back to the RAM. * DTC enable registers A to G, and I (DTCERA to DTCERG, DTCERI) * DTC vector register (DTVECR) Rev. 1.00 Jan. 29, 2008 Page 141 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.2.1 DTC Mode Register A (MRA) MRA is an 8-bit register that selects the DTC operating mode. Bit 7 6 Bit Name SM1 SM0 Initial Value Undefined Undefined R/W Description Source Address Mode 1 and 0 These bits specify an SAR operation after a data transfer. 0X: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 5 4 DM1 DM0 Undefined Undefined Destination Address Mode 1 and 0 These bits specify a DAR operation after a data transfer. 0X: DAR is fixed 10: DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) 11: DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 3 2 MD1 MD0 Undefined Undefined DTC Mode These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 1 DTS Undefined DTC Transfer Mode Select Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. 0: Destination side is repeat area or block area 1: Source side is repeat area or block area Rev. 1.00 Jan. 29, 2008 Page 142 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) Bit 0 Bit Name Sz Initial Value Undefined R/W Description DTC Data Transfer Size Specifies the size of data to be transferred. 0: Byte-size transfer 1: Word-size transfer [Legend] X: Don't care 8.2.2 DTC Mode Register B (MRB) MRB is an 8-bit register that selects the DTC operating mode. Bit 7 Bit Name CHNE Initial Value Undefined R/W Description DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 8.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER, are not performed. 6 DISEL Undefined DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time after the end of a data transfer. When this bit is set to 0, a CPU interrupt request is generated at the time when the specified number of data transfer ends. 5 to 0 Undefined Reserved These bits have no effect on DTC operation. Only 0 should be written to these bits. Rev. 1.00 Jan. 29, 2008 Page 143 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.2.3 DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 8.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts; the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. 8.2.6 DTC Transfer Count Register B (CRB) CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. Rev. 1.00 Jan. 29, 2008 Page 144 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.2.7 DTC Enable Registers A to G, and I (DTCERA to DTCERG) DTCER is comprised of seven registers; DTCERA to DTCERG, and is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 8.1. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Bit 7 6 5 4 3 2 1 0 Bit Name DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Activation Enable Setting this bit to 1 specifies a relevant interrupt source as a DTC activation source. [Clearing conditions] * * When the DISEL bit in MRB is 1 and the data transfer has ended When the specified number of transfers have ended These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not been completed. Rev. 1.00 Jan. 29, 2008 Page 145 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.2.8 DTC Vector Registers A to G (DTVECRA to DTVECRG) DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit 7 Bit Name SWDTE Initial Value 0 R/W R/W Description DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit. [Clearing conditions] * * When the DISEL bit is 0 and the specified number of transfers have not ended When 0 is written to the DISEL bit after a softwareactivated data transfer end interrupt (SWDTEND) request has been sent to the CPU. When the DISEL bit is 1 and data transfer has ended or when the specified number of transfers have ended, this bit will not be cleared. 6 5 4 3 2 1 0 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W DTC Software Activation Vectors 0 to 6 These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + (vector number x 2). For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. When the bit SWDTE is 0, these bits can be written. Rev. 1.00 Jan. 29, 2008 Page 146 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.3 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of RXI_0, for example, is the RDRF flag of SCI_0. When an interrupt has been designated a DTC activation source, the existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Figure 8.2 shows a block diagram of DTC activation source control. For details, see section 5, Interrupt Controller. Source flag cleared Clear controller Clear DTCER Select Clear request IRQ interrupt Interrupt request Selection circuit On-chip supporting module DTC DTVECR Interrupt controller Interrupt mask CPU Figure 8.2 Block Diagram of DTC Activation Source Control Rev. 1.00 Jan. 29, 2008 Page 147 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF). Register information should be located at an address that is a multiple of four within the range. Locating the register information in address space is shown in figure 8.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information. In the case of chain transfer, register information should be located in consecutive areas and the register information start address should be located at the vector address corresponding to the interrupt source as shown in figure 8.3. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] x 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is the same in both normal and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the register information start address. Lower address 0 Register information start address MRA MRB Chain transfer CRA MRA MRB CRA SAR DAR CRB Register information for 2nd transfer in chain transfer 1 2 SAR DAR CRB Register information 3 4 bytes Figure 8.3 Location of DTC Register Information in Address Space Rev. 1.00 Jan. 29, 2008 Page 148 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) Table 8.1 Interrupt Source Software External pin Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Source Write to DTVECR IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 DTC Vector Number Vector Address DTVECR 16 17 18 19 20 21 22 23 28 32 33 34 35 40 41 44 45 48 49 50 51 56 57 60 61 H'0400 + (vector number x 2) H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C H'042E H'0438 H'0440 H'0442 H'0444 H'0446 H'0450 H'0452 H'0458 H'045A H'0460 H'0462 H'0464 H'0466 H'0470 H'0472 H'0478 H'047A DTCE* DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED5 DTCED4 Low Priority High A/D counter TPU_0 Reserved for system use ADI (A/D conversion end) TGIA_0 TGIB_0 TGIC_0 TGID_0 TPU_1 TGIA_1 TGIB_1 TPU_2 TGIA_2 TGIB_2 TPU_3 TGIA_3 TGIB_3 TGIC_3 TGID_3 TPU_4 TGIA_4 TGIB_4 TPU_5 TGIA_5 TGIB_5 Rev. 1.00 Jan. 29, 2008 Page 149 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) Interrupt Source Origin of Interrupt Source Reserved for system use DTC Vector Number Vector Address 64 65 68 69 H'0480 H'0482 H'0488 H'048A H'0490 H'0492 H'0494 H'0496 H'04A2 H'04A4 H'04AA H'04AC H'04B2 H'04B4 H'04B8 H'04BA H'04C0 H'04C2 H'04C8 H'04CC H'04D0 H'04D2 H'04D4 H'04D6 H'04D8 H'04DA DTCE* DTCED3 DTCED2 DTCED1 DTCED0 DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEF1 DTCEF0 DTCEG7 DTCEG6 DTCEG5 DTCEG4 DTCEG3 DTCEG2 Priority High Reserved for system use 72 73 74 75 SCI_0 RXI_0 TXI_0 81 82 85 86 89 90 92 93 96 97 100 102 104 105 106 107 108 109 SCI_1 RXI_1 TXI_1 SCI_2 IIC-0 IIC-1 RXI_2 TXI_2 Reserved for system use Reserved for system use IICI0 IICI1 Motor control CMI1 PWM CMI2 Note: * Reserved for system use Reserved for system use Low DTCE bits with no corresponding interrupt are reserved, and the write value should always be 0. Rev. 1.00 Jan. 29, 2008 Page 150 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.5 Operation Register information is stored in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to the on-chip RAM. The pre-storage of register information in the on-chip RAM makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, and block transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed depending on its register information. Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE=1 No Yes Transfer Counter=0 or DISEL=1 No Clear an activation flag Yes Clear DTCER End Interrupt exception handling Figure 8.4 Flowchart of DTC Operation Rev. 1.00 Jan. 29, 2008 Page 151 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. Table 8.2 lists the register information in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt can be requested. Table 8.2 Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Register Information in Normal Mode Abbreviation SAR DAR CRA CRB Function Designates source address Designates destination address Designates transfer count Not used SAR Transfer DAR Figure 8.5 Memory Mapping in Normal Mode Rev. 1.00 Jan. 29, 2008 Page 152 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 8.3 lists the register information in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 8.3 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Repeat Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds number of transfers Designates transfer count Not used SAR or DAR Repeat area Transfer DAR or SAR Figure 8.6 Memory Mapping in Repeat Mode Rev. 1.00 Jan. 29, 2008 Page 153 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 8.4 lists the register information in block transfer mode. The block size can be between 1 and 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have been completed, a CPU interrupt is requested. Table 8.4 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Block Transfer Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds block size Designates block size count Transfer count Rev. 1.00 Jan. 29, 2008 Page 154 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) First block SAR or DAR Block area Transfer DAR or SAR Nth block Figure 8.7 Memory Mapping in Block Transfer Mode Rev. 1.00 Jan. 29, 2008 Page 155 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.8 shows the outline of the chain transfer operation. When activated, the DTC reads the register information start address stored at the vector address corresponding to the activation source, and then reads the first register information at that start address. After data transfer ends, the CHNE bit will be tested. When it has been set to 1, DTC reads the next register information located in a consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit is cleared to 0. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. Source Destination Register information CHNE=1 DTC vector address Register information start address Register information CHNE=0 Source Destination Figure 8.8 Chain Transfer Operation Rev. 1.00 Jan. 29, 2008 Page 156 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.5.5 Interrupts An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has been completed, or the specified number of transfers have been completed, after data transfer ends the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 8.5.6 DTC activation request DTC request Data transfer Read Write Operation Timing Vector read Address Transfer information read Transfer information write Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode) Rev. 1.00 Jan. 29, 2008 Page 157 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) DTC activation request DTC request Vector read Address Data transfer Read Write Read Write Transfer information read Transfer information write Figure 8.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) DTC activation request DTC request Vector read Address Read Write Read Write Data transfer Data transfer Transfer information read Transfer information write Transfer information read Transfer information write Figure 8.11 DTC Operation Timing (Example of Chain Transfer) Rev. 1.00 Jan. 29, 2008 Page 158 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.5.7 Number of DTC Execution States Table 8.5 lists execution status for a single DTC data transfer, and table 8.6 shows the number of states required for each execution status. Table 8.5 DTC Execution Status Vector Read I 1 1 1 Register Information Read/Write Data Read J K 6 6 6 1 1 N Data Write L 1 1 N Internal Operations M 3 3 3 Mode Normal Repeat Block transfer [Legend] N: Block size (initial setting of CRAH and CRAL) Table 8.6 Number of States Required for Each Execution Status OnChip RAM 32 1 1 1 1 1 1 1 OnChip On-Chip I/O ROM Registers 16 1 1 1 1 1 1 8 2 2 4 2 4 16 2 2 2 2 2 Object to be Accessed Bus width Access states Execution status Vector read SI Register information read/write SJ Byte data read SK Word data read SK Byte data write SL Word data write SL Internal operation SM Note: * Not available in this LSI. External Devices* 8 2 4 2 4 2 4 3 3+m 16 2 2 3 3+m 3+m 3+m 3+m 3+m 6+2m 2 6+2m 2 3+m 2 6+2m 2 The number of execution states is calculated from using the formula below. Note that is the sum of all transfers activated by one activation source (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * (1 + SI) + (J * SJ + K * SK + L * SL) + M * SM Rev. 1.00 Jan. 29, 2008 Page 159 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) For example, when the DTC vector address table is located in the on-chip ROM, normal mode is set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. 8.6 8.6.1 Procedures for Using DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. 2. 3. 4. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. Set the start address of the register information in the DTC vector address. Set the corresponding bit in DTCER to 1. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. 5. After one data transfer has been completed, or after the specified number of data transfers have been completed, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software 8.6.2 The procedure for using the DTC with software activation is as follows: 1. 2. 3. 4. 5. 6. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. Set the start address of the register information in the DTC vector address. Check that the SWDTE bit is 0. Write 1 to SWDTE bit and the vector number to DTVECR. Check the vector number written to DTVECR. After one data transfer has been completed, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have been completed, the SWDTE bit is held at 1 and a CPU interrupt is requested. Rev. 1.00 Jan. 29, 2008 Page 160 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.7 8.7.1 Examples of Use of the DTC Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where data will be received in DAR, and 128 (H0080) in CRA. CRB can be set to any value. 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time the reception of one byte of data has been completed on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have been completed, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine will perform wrap-up processing. Rev. 1.00 Jan. 29, 2008 Page 161 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.7.2 Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). 1. Perform settings for transfer to the PPG's NDR. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), a fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. 2. Perform settings for transfer to the TPU's TGR. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), a fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. 3. Locate the TPU transfer register information consecutively after the NDR transfer register information. 4. Set the start address of the NDR transfer register information to the DTC vector address. 5. Set the bit corresponding to TGIA in DTCER to 1. 6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. 7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. 8. Set the CST bit in TSTR to 1, and start the TCNT count operation. 9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. Rev. 1.00 Jan. 29, 2008 Page 162 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.7.3 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. 2. Set the start address of the register information at the DTC vector address (H'04C0). 3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. 4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. 5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. 7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. Rev. 1.00 Jan. 29, 2008 Page 163 of 666 REJ09B0427-0100 Section 8 Data Transfer Controller (DTC) 8.8 8.8.1 Usage Notes Module Stop Mode Setting DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be enabled. Register access is disabled by setting module stop mode. Note that module stop mode cannot be set during DTC being activated. For details, refer to section 21, Power-Down Modes. 8.8.2 On-Chip RAM The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. 8.8.3 DTCE Bit Setting For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register. Rev. 1.00 Jan. 29, 2008 Page 164 of 666 REJ09B0427-0100 Section 9 I/O Ports Section 9 I/O Ports This LSI has 10 I/O ports (ports 1 to 3, A to F, H, and J), and two input-only port (ports 4 and 9). Table 9.1 shows the port functions. The pins of each port also have other functions. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR or DDR register. Ports A to E have a built-in pull-up MOS function, and in addition to DR and DDR, have a MOS input pull-up control register (PCR) to control the on/off state of MOS input pull-up. Ports 3, and A to C include an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. When ports 10 to 13 and A to F are used as the output pins for expanded bus control signals, they can drive one TTL load plus a 90pF capacitance load. Ports other than those can drive one TTL load and a 30pF capacitance load. All I/O ports can drive Darlington transistors when set to output. Ports 1 and A to C can drive an LED (10 mA sink current). Rev. 1.00 Jan. 29, 2008 Page 165 of 666 REJ09B0427-0100 Section 9 I/O Ports Table 9.1 Port Port 1 Port Functions Description General I/O port also functioning as TPU I/O pins, PPG and address output pins, and interrupt input pins Mode 4 Mode 5 Mode 6 Mode 7 P17/PO15/TIOCB2/ TCLKD P16/PO14/TIOCA2/ IRQ1 P15/PO13/TIOCB1/ TCLKC P14/PO12/TIOCA1/IRQ0 P13/PO11/TIOCD0/ TCLKB P12/O10/TIOCC0/ TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 Input/Output Type P17/PO15/TIOCB2/TCLKD P16 /PO14/TIOCA2/IRQ1 P15 /PO13/TIOCB1/TCLKC P14 /PO12/TIOCA1/IRQ0 P13 /PO11/TIOCD0/TCLKB/A23 P12 /PO10/TIOCC0/TCLKA/A22 P11/PO9/TIOCB0/A21 P10/PO8/TIOCA0/A20 Port 3 General I/O port also functioning as SCI and IIC I/O pins, and interrupt input pins P35/SCK1/SCL0/IRQ5 P34/RxD1/SDA0 P33/TxD1/SCL1 P32/SCK0/SDA1/IRQ4 P31/RxD0 P30/TxD0 Open-drain output Port 4 General input port also functioning as A/D analog input pins and D/A analog output pins P47/AN7/DA1 P46/AN6/DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Rev. 1.00 Jan. 29, 2008 Page 166 of 666 REJ09B0427-0100 Section 9 I/O Ports Port Port 9 Description General input port also functioning as analog input pins Mode 4 P97/AN15 P96/AN14 P95/AN13 P94/AN12 P93/AN11 P92/AN10 P91/AN9 P90/AN8 Mode 5 Mode 6 Mode 7 Input/Output Type Port A General I/O port PA3/A19/SCK2 also functioning as PA2/A18/RxD2 SCI I/O pins and address output pins PA1/A17/TxD2 PA0/A16 PA3/SCK2 PA2/RxD2 PA1/TxD2 PA0 PB7/TIOCB5 PB6/TIOCA5 PB5/TIOCB4 PB4/TIOCA4 PB3/TIOCD3 PB2/TIOCC3 PB1/TIOCB3 PB0/TOICA3 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Built-in pull-up MOS Open-drain output Built-in pull-up MOS Open-drain output Port B General I/O port PB7/A15/TIOCB5 also functioning as PB6/A14/TIOCA5 TPU I/O pins and address output pins PB5/A13/TIOCB4 PB4/A12/TIOCA4 PB3/A11/TIOCD3 PB2/A10/TIOCC3 PB1/A9/TIOCB3 PB0/A8/TOICA3 Port C PC7/A7 General I/O port also functioning as PC6/A6 address output pins PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 Built-in pull-up MOS Open-drain output Rev. 1.00 Jan. 29, 2008 Page 167 of 666 REJ09B0427-0100 Section 9 I/O Ports Port Port D Description General I/O port also functioning as data I/O pins Mode 4 D15 D14 D13 D12 D11 D10 D9 D8 Mode 5 Mode 6 Mode 7 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF7/ PF6 PF5 PF4 PF3/ADTRG/IRQ3 PF0/IRQ2 Input/Output Type Built-in pull-up MOS Port E General I/O port also functioning as data I/O pins PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0 /D0 Built-in pull-up MOS Port F General I/O port also functioning as output pin, bus control I/O pins, and interrupt input pins PF7/ PF6/AS PF5/RD PF4/HWR PF3/LWR/ADTRG/IRQ3 PF0/IRQ2 Rev. 1.00 Jan. 29, 2008 Page 168 of 666 REJ09B0427-0100 Section 9 I/O Ports Port Port H Description General I/O port also functioning as PWM output pins Mode 4 Mode 5 Mode 6 Mode 7 Input/Output Type PH7/PWM1H PH6/PWM1G PH5/PWM1F PH4/PWM1E PH3/PWM1D PH2/PWM1C PH1/PWM1B PH0/PWM1A Port J General I/O port also functioning as PWM output pins PJ7/PWM2H PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E PJ3/PWM2D PJ2/PWM2C PJ1/PWM2B PJ0/PWM2A Rev. 1.00 Jan. 29, 2008 Page 169 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.1 Port 1 Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins, TPU I/O pins, address output pins, and external interrupt pins. * Port 1 data direction register (P1DDR) * Port 1 data register (P1DR) * Port 1 register (PORT1) 9.1.1 Port 1 Data Direction Register (P1DDR) P1DDR is a write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. Rev. 1.00 Jan. 29, 2008 Page 170 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description An output data for a pin is stored when the pin function is specified to a general purpose output port. 9.1.3 Port 1 Register (PORT1) PORT1 shows the pin states. It cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name P17 P16 P15 P14 P13 P12 P11 P10 Initial Value * * * * * * * * R/W R R R R R R R R Description If this register read is performed while P1DDR bits are set to 1, the P1DR values are read. If this register read is performed while P1DDR bits are cleared to 0, the pin states are read. Determined by state of pins P17 to P10. Rev. 1.00 Jan. 29, 2008 Page 171 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.1.4 Pin Functions The correspondence between the register specification and the pin functions is shown below. * P17/PO15/TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in NDERH, and bit P17DDR. TPU Channel 2 Setting P17DDR NDER15 Pin function Table below (1) TIOCB2 output 0 P17 input Table below (2) 1 0 P17 output TIOCB2 input* TCLKD input*2 1 1 1 PO15 output TPU channel 2 setting MD3 to MD0 IOB3 to IOB0 (2) (1) B'0000, B'01xx (2) B'0010 (2) (1) B'0011 (2) B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 [Legend] x: Don't care Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 = 1. 2. TCLKD input when the setting for either TCR_0 or TCR_5 is: TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. Rev. 1.00 Jan. 29, 2008 Page 172 of 666 REJ09B0427-0100 Section 9 I/O Ports * P16/PO14/TIOCA2/IRQ1 The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH, and bit P16DDR. TPU channel 2 setting P16DDR NDER14 Pin function Table below (1) TIOCA2 output 0 P16 input Table below (2) 1 0 P16 output TIOCA2 input* IRQ1 input TPU channel 2 setting MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx B'0000 B'0100 B'1xxx CCLR1, CCLR0 Output function Output compare output PWM mode 1 output*2 Other than B'01 PWM mode 2 output B'01 B'0001 to B'0011 B'0101 to B'0111 (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 Other than B'xx00 (2) 1 1 1 PO14 output [Legend] x: Don't care Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 = 1. 2. TIOCB2 output is disabled. Rev. 1.00 Jan. 29, 2008 Page 173 of 666 REJ09B0427-0100 Section 9 I/O Ports * P15/PO13/TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH, and bit P15DDR. TPU channel 1 setting P15DDR NDER13 Pin function Table below (1) TIOCB1 output 0 P15 input Table below (2) 1 0 P15 output TIOCB1 input*1 TCLKC input*2 1 1 PO13 output TPU channel 1 setting MD3 to MD0 IOB3 to IOB0 (2) (1) B'0000, B'01xx (2) B'0010 (2) (1) B'0011 (2) B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 Output compare output B'xx00 Other than B'xx00 CCLR1, CCLR0 Output function Other than B'10 PWM mode 2 output B'10 [Legend] x: Don't care Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 to IOB0 = B'10xx. 2. TCLKC input when the setting for either TCR_0 or TCR_2 is: TPSC2 to TPSC0 = B'110; or when the setting for either TCR_4 or TCR_5 is TPSC2 to TPSC0 = B'101. TCLKC input when channels 2 and 4 are set to phase counting mode. Rev. 1.00 Jan. 29, 2008 Page 174 of 666 REJ09B0427-0100 Section 9 I/O Ports * P14/PO12/TIOCA1/IRQ0 The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH, and bit P14DDR. TPU channel 1 setting P14DDR NDER12 Pin function Table below (1) TIOCA1 output 0 P14 input Table below (2) 1 0 P14 output TIOCA1 input* IRQ0 input TPU channel 1 setting MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx B'0000 B'0100 B'1xxx CCLR1, CCLR0 Output function Output compare output PWM mode 1 output*2 Other than B'01 PWM mode 2 output B'01 B'0001 to B'0011 B'0101 to B'0111 (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 Other than B'xx00 (2) 1 1 1 PO12 output [Legend] x: Don't care Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to IOA0 = B'10xx. 2. TIOCB1 output is disabled. Rev. 1.00 Jan. 29, 2008 Page 175 of 666 REJ09B0427-0100 Section 9 I/O Ports * P13/PO11/TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the operating mode, bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIORL_0, the TPU channel 0 setting (by bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bits AE3 to AE0 in PFCR, and bit P13DDR. Operating mode AE3 to AE0 TPU channel 0 setting P13DDR NDER11 Pin function Table below (1) TIOCD0 output 0 P13 input Modes 4 to 6 B'0000 to B'1110 Table below (2) 1 0 P13 output TIOCD0 input* TCLKB input* 2 1 B'1111 1 1 PO11 output A23 input Operating mode AE3 to AE0 TPU channel 0 setting P13DDR NDER11 Pin function Table below (1) TIOCD0 output 0 P13 input Modes 7 Table below (2) 1 0 P13 output TIOCD0 input* TCLKB input*2 1 1 1 PO11 output Rev. 1.00 Jan. 29, 2008 Page 176 of 666 REJ09B0427-0100 Section 9 I/O Ports TPU channel 0 setting MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000 B'0100 B'1xxx (1) (2) B'0010 (2) (1) B'0011 (2) B'0001 to B'0011 B'0101 toB'0111 Output compare output B'xx00 Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'110 PWM mode 2 output B'110 [Legend] x: Don't care Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 = B'10xx. 2. TCLKB input when the setting for TCR_0 to TCR_2 is: TPSC2 to TPSC0 = B'101. TCLKB input when channels 1 and 5 are set to phase counting mode. Rev. 1.00 Jan. 29, 2008 Page 177 of 666 REJ09B0427-0100 Section 9 I/O Ports * P12/PO10/TIOCC0/TCLKA/A22 The pin function is switched as shown below according to the combination of the operating mode, bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIORL_0, the TPU channel 0 setting (by bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bits AE3 to AE0 in PFCR, and bit P12DDR. Operating mode AE3 toAE0 TPU channel 0 setting P12DDR NDER10 Pin function Modes 4 to 6 B'0000 to B'1110 Table below (1) TIOCC0 output 0 P12 input Table below (2) 1 0 P12 output 2 B'1111 1 1 PO10 output A22 output TIOCC0 input*1 TCLKA input* Operating mode AE3 to AE0 TPU channel 0 setting P12DDR NDER10 Pin function Table below (1) TIOCC0 output 0 P12 input Modes 7 Table below (2) 1 0 P12 output TIOCC0 input* TCLKA input*2 1 1 1 PO10 output Rev. 1.00 Jan. 29, 2008 Page 178 of 666 REJ09B0427-0100 Section 9 I/O Ports TPU Channel0 Setting MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000 B'0100 B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 (1) B'0011 (2) B'0001 to B'0011 B'0101 to B'0111 Output compare output Other than B'xx00 CCLR2 to CCLR0 Output function PWM mode 1 output*3 Other than B'101 PWM mode 2 output B'101 [Legend] x: Don't care Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx. 2. TCLKA input when the setting for TCR_0 to TCR_5 is: TPSC2 to TPSC0 = B'100. TCLKA input when channels 1 and 5 are set to phase counting mode. 3. TIOCD0 output is disabled. When BFA = 1 or BFB = 1 in TMDR_0, output is disabled and setting (2) applies. Rev. 1.00 Jan. 29, 2008 Page 179 of 666 REJ09B0427-0100 Section 9 I/O Ports * P11/PO9/TIOCB0/A21 The pin function is switched as shown below according to the combination of the operating mode, bits MD3 to MD0 in TMDR0, the TPU channel 0 setting (by bits IOB3 to IOB0 in TIORH_0, bits AE3 to AE0 in PFCR, bit NDER9 in NDERH and bit P11DDR. Operating mode AE3 toAE0 TPU channel 0 setting P11DDR NDER9 Pin function Modes 4 to 6 B'0000 to B'1101 Table below (1) TIOCB0 output 0 P11 input Table below (2) 1 0 P11 output 1 1 PO9 output B'1111 to B'1111 A21 output TIOCB0 input*1 Operating mode AE3 to AE0 TPU channel 0 setting P11DDR NDER9 Pin function Table below (1) TIOCB0 output 0 P11 input Modes 7 Table below (2) 1 0 P11 output TIOCB0 input*1 1 1 PO9 output Rev. 1.00 Jan. 29, 2008 Page 180 of 666 REJ09B0427-0100 Section 9 I/O Ports TPU channel 0 setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0000 B'0100 B'1xxx (1) (2) B'0010 (2) (1) B'0011 (2) B'0001 to B'0011 B'0101 toB'0111 Output compare output B'xx00 Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'010 PWM mode 2 output B'010 [Legend] x: Don't care Note: * TIOCB0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx. Rev. 1.00 Jan. 29, 2008 Page 181 of 666 REJ09B0427-0100 Section 9 I/O Ports * P10/PO8/TIOCA0/A20 The pin function is switched as shown below according to the combination of the operating mode, bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIORH_0, the TPU channel 0 setting (by bits CCLR2 to CCLR0 in TCR0), bits AE3 to AE0 in PFCR, bit NDER8 in NDERH and bit P10DDR. Operating mode AE3 toAE0 TPU channel 0 setting P10DDR NDER8 Pin function Modes 4 to 6 B'0000 to B'1100 Table below (1) TIOCA0 output 0 P10 input Table below (2) 1 0 P10 output 1 1 PO8 output B'1101 to B'1111 A20 output TIOCA0 input*1 Operating mode AE3 to AE0 TPU channel 0 setting P10DDR NDER8 Pin function Table below (1) TIOCA0 output 0 P10 input Mode 7 Table below (2) 1 0 P10 output TIOCA0 input*1 1 1 PO8 output Rev. 1.00 Jan. 29, 2008 Page 182 of 666 REJ09B0427-0100 Section 9 I/O Ports TPU Channel 0 Setting MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000 B'0100 B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0001 to B'0011 B'0101 to B'0111 Output compare output Other than B'xx00 CCLR2 to CCLR0 Output function -- PWM mode 1 output*2 Other than B'001 PWM mode 2 output B'001 -- [Legend] x: Don't care Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx. 2. TIOCB0 output is disabled. Rev. 1.00 Jan. 29, 2008 Page 183 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.2 Port 3 Port 3 is a 6-bit I/O port. Port 3 pins also function as IIC I/O pins, SCI I/O pins and external interrupt input pins. All of the port 3 pin functions have the same operating mode. * * * * Port 3 data direction register (P3DDR) Port 3 data register (P3DR) Port 3 register (PORT3) Port 3 open-drain control register (PORT3) Port 3 Data Direction Register (P3DDR) 9.2.1 P3DDR is a write-only register, the individual bits of which specify input or output for the pins of port 3. P3DDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial Value R/W Description Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. Undefined Undefined 0 0 0 0 0 0 W W W W W W Rev. 1.00 Jan. 29, 2008 Page 184 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.2.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit 7 6 5 4 3 2 1 0 Bit Name P35DR P34DR P33DR P32DR P31DR P30DR Initial Value R/W Description An output data for a pin is stored when the pin function is specified to a general purpose output port. Undefined Undefined 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W 9.2.3 Port 3 Register (PORT3) PORT3 shows the pin states. It cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name P35 P34 P33 P32 P31 P30 Initial Value R/W Description If this register read is performed while P3DDR bits are set to 1, the P3DR values are read. If this register read is performed while P3DDR bits are cleared to 0, the pin states are read. Undefined Undefined * * * * * * R R R R R R Determined by state of pins P35 to P30. Rev. 1.00 Jan. 29, 2008 Page 185 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.2.4 Port 3 Open-Drain Control Register (P3ODR) P3ODR controls output of port 3. Bit 7 6 5 4 3 2 1 0 Bit Name P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Initial Value R/W Description By setting P3ODR to 1, the port 3 pins become an NMOS open drain output, and when cleared to 0 they become CMOS output. Undefined Undefined 0 0 0 0 0 0 R R R R R R 9.2.5 Pin Functions The correspondence between the register specification and the pin functions is shown below. * P35/SCK1/SCL0/IRQ5 The pin function is switched as shown below according to the combination of the ICE bit in ICCR0 of IIC_0, the C/A bit in SMR of SCI_1, the CKE0 and CKE1 bits in SCR, and the P35DDR bit. ICE CKE1 C/A CKE0 P35DDR Pin function 0 P35 input 0 1 P35 output 0 1 SCK1 output* 0 1 SCK1 output* 0 1 SCK1 input 1 0 0 0 SCLO I/On IRQ5 input Note: * When P35ODR = 1, it becomes NMOS open drain output. Rev. 1.00 Jan. 29, 2008 Page 186 of 666 REJ09B0427-0100 Section 9 I/O Ports * P34/RxD1/SDA0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR0 of ICC_0, the RE bit in SCR of SCI_1 and P34DDR bit. ICE RE P34DDR Pin function Note: * 0 P34 input 0 1 P34 output* 0 1 RxD1 input 1 SDA0 I/O When P34ODR = 1, it becomes NMOS open drain output. * P33/TxD1/SCL1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR1 of ICC_1, the TE bit in SCR of SCI_1 and P33DDR bit. ICE TE P33DDR Pin function Note: * 0 P33 input 0 1 P33 output* 0 1 TxD1 output 1 SCL1 I/O When P33ODR = 1, it becomes NMOS open drain output. * P32/SCK0/SDA1/IRQ4 The pin function is switched as shown below according to the combination of the ICE bit in ICCR1 of ICC_1, the C/A bit in SMR of SCI_0, the CKE0 and CKE1 bits in SCR, and the P32DDR bit. ICE CKE1 C/A CKE0 P32DDR Pin function 0 P32 input 0 1 P32 output 0 1 SCK0 output* 0 0 1 1 1 0 0 0 SDA1 I/O SCK0 output SCK0 input pin* IRQ4 input Note: * When P32ODR = 1, it becomes NMOS open drain output. Rev. 1.00 Jan. 29, 2008 Page 187 of 666 REJ09B0427-0100 Section 9 I/O Ports * P31/RxD0 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_0 and P31DDR bit. RE P31DDR Pin function Note: * 0 P31 input 0 1 P31 output* 1 RxD0 input When P31ODR = 1, it becomes NMOS open drain output. * P30/TxD0 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_0 and P30DDR bit. TE P30DDR Pin function Note: * 0 P30 input 0 1 P30 output* 1 TxD0 output pin When P30ODR = 1, it becomes NMOS open drain output. Rev. 1.00 Jan. 29, 2008 Page 188 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.3 Port 4 Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins and D/A converter analog output pins. Port 4 pin functions are the same in all operating modes. * Port 4 Register (PORT4) 9.3.1 Port 4 Register (PORT4) PORT4 is a read-only register that shows the pin states. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name P47 P46 P45 P44 P43 P42 P41 P40 Initial Value * * * * * * * * R/W R R R R R R R R Description The pin states are always read when PORT4 read is performed. Determined by state of pins P47 to P40. 9.3.2 Pin Functions Port 4 also functions as A/D converter analog input pins and D/A converter analog output pins. Rev. 1.00 Jan. 29, 2008 Page 189 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.4 Port 9 Port 9 is a 4-bit input-only port. Port 9 pins also function as A/D converter analog input pins. Port 9 pin functions are the same in all operating modes. * Port 9 Register (PORT9) 9.4.1 Port 9 Register (PORT9) PORT9 is a read-only register that shows the pin states. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name P93 P92 P91 P90 Initial Value * * * * * * * * R/W R R R R Description The pin states are always read when PORT9 read is performed. Determined by state of pins P93 to P90. 9.4.2 Pin Functions Port 9 also functions as A/D converter analog input pins. Rev. 1.00 Jan. 29, 2008 Page 190 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.5 Port A Port A is a 4-bit I/O port. Port A also functions as address bus output pins and SCI-3 I/O pins. The pin functions change according to the operating mode. Port A has a built-in MOS input pull-up function that can be controlled by software. * * * * * Port A data direction register (PADDR) Port A data register (PADR) Port A register (PORTA) Port A pull-up MOS control register (PAPCR) Port A open-drain control register (PAODR) Port A Data Direction Register (PADDR) 9.5.1 PADDR is a register, the individual bits of which specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PA3DDR PA2DDR PA1DDR PA0DDR Initial Value R/W Description Mode 7: Setting a PADDR bit to 1 makes the corresponding port A pin an output port, and clearing a bit to 0 makes the corresponding pin an input port. Modes 4 to 6: The port A pins function as address outputs as specified by the setting of bits AE3 to AE0 of PFCR, regardless of the values of bits PA7DDR to PA0DDR. Also, when the pins are not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an output port, and clearing a bit to 0 makes the corresponding pin an input port. Undefined Undefined Undefined Undefined 0 0 0 0 W W W W Rev. 1.00 Jan. 29, 2008 Page 191 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.5.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value PA3DR PA2DR PA1DR PA0DR R/W Description An output data for a pin is stored when the pin function is specified to a general purpose output port. Undefined Undefined Undefined Undefined 0 0 0 0 R/W R/W R/W R/W 9.5.3 Port A Register (PORTA) PORTA shows the pin states. It cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: * Initial Bit Name Value PA3 PA2 PA1 PA0 R/W Description If this register read is performed while PADDR bits are set to 1, the PADR values are read. If this register read is performed while PADDR bits are cleared to 0, the pin states are read. Undefined Undefined Undefined Undefined * * * * R R R R Determined by state of pins PA3 to PA0. Rev. 1.00 Jan. 29, 2008 Page 192 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.5.4 Port A Pull-Up MOS Control Register (PAPCR) PAPCR controls the MOS input pull-up function incorporated into port A on an individual bit basis. Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value PA3PCR PA2PCR PA1PCR PA0PCR R/W Description In modes 4 to 6, if a pin is in the input state in accordance with the settings of SCMR, SMR, SCR, and PADDR in PFCR and SCI_2, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. In mode 7, if a pin is in the input state in accordance with the setting of SCMR, SMR, SCR, and PADDR in SCI_2, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. Undefined Undefined Undefined Undefined 0 0 0 0 R/W R/W R/W R/W 9.5.5 Port A Open-Drain Control Register (PAODR) PAODR controls output of port A. Bit 7 6 5 4 3 2 1 0 Initial Bit Name Value R/W Description When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR, setting a PAODR bit makes the corresponding port A pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. Undefined Undefined Undefined Undefined R/W R/W R/W R/W PA3ODR 0 PA2ODR 0 PA1ODR 0 PA0ODR 0 Rev. 1.00 Jan. 29, 2008 Page 193 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.5.6 Pin Functions Port A pins also function as SCI2 I/O pins and address bus output pins. * PA3/A19/SCK2 The pin function is switched as shown below according to the combinations of the operating mode, bits AE3 to AE0 in PFCR, the C/A bit in SMR of SCI2, the CKE0 and CKE1 bits in SCR, and the PA3DDR bit. Operating mode AE3 to AE0 CKE1 C/A CKE0 PA3DDR Pin function Operating mode CKE1 C/A CKE0 PA3DDR Pin function 0 PA3 input 0 1 PA3 output 0 1 SCK2 output 0 1 SCK2 output 0 PA3 input 0 1 0 1 Modes 4 to 6 B'0000 to B'1011 0 1 1 B'1100 to B'1111 A19 output PA3 output SCK2 output SCK2 output SCK2 input Mode 7 1 SCK2 input Rev. 1.00 Jan. 29, 2008 Page 194 of 666 REJ09B0427-0100 Section 9 I/O Ports * PA2/A18/RxD2 The pin function is switched as shown below according to the combinations of the operating mode, bits AE3 to AE0 in PFCR, the RE bit in SCR of SCI2 and the bit PA2DDR. Operating mode AE3 to AE0 RE PA2DDR Pin function 0 PA2 input 0 1 PA2 output Modes 4 to 6 B'0000to B'1010 1 RxD2 input B'1011 to B'1111 A18 output Operating mode RE PA2DDR Pin function 0 PA2 input 0 Mode 7 1 1 PA2 output RxD2 input * PA1/A17/TxD2 The pin function is switched as shown below according to the combinations of the operating mode, bits AE3 to AE0 in PFCR, the TE bit in SCR of SCI2 and the bit PA1DDR. Operating mode AE3 to AE0 TE PA1DDR Pin function 0 PA1 input 0 1 PA1 output Modes 4 to 6 B'0000to B'1001 1 TxD2 input B'1010 to B'1111 A17 output Operating mode TE PA1DDR Pin function 0 PA1 input 0 Mode 7 1 1 PA1 output TxD2 input Rev. 1.00 Jan. 29, 2008 Page 195 of 666 REJ09B0427-0100 Section 9 I/O Ports * PA0/A16 The pin function is switched as shown below according to the combinations of the operating mode, bits AE3 to AE0 in PFCR and the bit PA0DDR. Operating mode AE3 to AE0 PA0DDR Pin function 0 PA0 input Modes 4 to 6 B'0000 to B'1000 1 PA0 output A16 output B'1001 to B'1111 Operating mode PA0DDR Pin function 0 PA0 input Mode 7 1 PA0 output Rev. 1.00 Jan. 29, 2008 Page 196 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.6 Port B Port B is an 8-bit I/O port. Port B also functions as TPU I/O pins and address bus output pins. The pin functions are determined by the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. * * * * * Port B data direction register (PBDDR) Port B data register (PBDR) Port B register (PORTB) Port B pull-up MOS control register (PBPCR) Port B open-drain control register (PBODR) Port B Data Direction Register (PBDDR) 9.6.1 PBDDR is a write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In modes 4 to 6, in accordance with the setting in the bits AE3 to AE0 in PFCR, corresponding port B pin is an output pin regardless of the PBDDR setting. When pins are not address outputs, setting a DDR bit to 1 makes the corresponding port B pin an output pin, while clearing the bit to 0 makes the pin a an input pin. In mode 7, setting a PBDDR bit makes the corresponding port B pin an output pin, while clearing the bit to 0 makes the pin an input pin. Rev. 1.00 Jan. 29, 2008 Page 197 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.6.2 Port B Data Register (PBDR) PBDR stores output data for the port B pins. Bit 7 6 5 4 3 2 1 0 Bit Name PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description An output data for a pin is stored when the pin function is specified to a general purpose output port. 9.6.3 Port B Register (PORTB) PORTB shows the pin states. It cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial Value * * * * * * * * R/W R R R R R R R R Description If this register read is performed while PBDDR bits are set to 1, the PBDR values are read. If this register read is performed while PBDDR bits are cleared to 0, the pin states are read. Determined by state of pins PB7 to PB0. Rev. 1.00 Jan. 29, 2008 Page 198 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.6.4 Port B Pull-Up MOS Control Register (PBPCR) PBPCR controls the MOS input pull-up function incorporated into port B on an individual bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, TIOR of TPU, and in PBDDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. In mode 7, if a pin is in the input state in accordance with the setting in TIOR of TPU and in PBDDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. 9.6.5 Port B Open-Drain Control Register (PBODR) PBODR controls output of port B. Bit 7 6 5 4 3 2 1 0 Bit Name PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR, setting a PBODR bit to 1 makes the corresponding port B pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. Rev. 1.00 Jan. 29, 2008 Page 199 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.6.6 Pin Functions The correspondence between the register specification and the pin functions is shown below. * PB7/A15/TIOCB5 The pin function is switched as shown below according to the combination of the operating mode, bits AE3 to AE0 in PFCR, bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, the TPU channel 5 setting (by bits CCLR1 and CCLR0 in TCR_5), and bit PB7DDR. Operating mode AE3 to AE0 TPU channel 5 setting PB7DDR Pin function Table below (1) TIIOCB5 output 0 PB7 input Modes 4 to 6 B'0000 to B'0111 Table below (2) 1 PB7 output B'1000 to B'1111 A15 Output TIOCB5 input* Operating mode TPU channel 5 setting PB7DDR Pin function Table below (1) TIOCB5 output 0 PB7 input TIOCB5 input* TPU channel 5 setting MD3 to MD0 IOB3 to IOB0 (2) (1) B'0000, B'01xx B'0000 B'0100 B'1xxx CCLR1, CCLR0 Output function [Legend] Note: * Output compare input Other than B'10 PWM mode 2 output B'10 B0001 to B'0011 B'0101 to B'0111 (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) Mode 7 Table below (2) 1 PB7 output x: Don't care TIOCB5 input when MD3 to MD0=B'0000, B'01xx, and IOB3=1. Rev. 1.00 Jan. 29, 2008 Page 200 of 666 REJ09B0427-0100 Section 9 I/O Ports * PB6/A14/TIOCA5 The pin function is switched as shown below according to the combination of the operating mode, bits AE3 to AE0 in PFCR, bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, the TPU channel 5 setting (by bits CCLR1 and CCLR0 in TCR_5), and bit PB6DDR. Operating mode AE3 to AE0 TPU channel 5 setting PB6DDR Pin function Table below (1) TIOCA5 output 0 PB6 input 1 Modes 4 to 6 B'0000 to B'0110 Table below (2) 1 PB6 output B'0111 to B'1111 A14 Output TIOCA5 input* Operating mode TPU channel 5 setting PB6DDR Pin function Table below (1) TIOCA5 output 0 PB6 input Mode 7 Table below (2) 1 PB6 output TIOCA5 input*1 TPU channel 5 setting MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111' Output compare output Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 B'01 PWM mode 1 PWM mode 2 2 output output* [Legend] x: Don't care Notes: 1. TIOCA5 input when MD3 to MD0=B'0000, B'01xx, and IOA3=1. 2. TIOCB5 is disabled. Rev. 1.00 Jan. 29, 2008 Page 201 of 666 REJ09B0427-0100 Section 9 I/O Ports * PB5/A13/TIOCB4 The pin function is switched as shown below according to the combination of the operating mode, bits AE3 to AE0 in PFCR, bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, the TPU channel 4 setting (by bits CCLR1 and CCLR0 in TCR_4), and bit PB5DDR. Operating mode AE3 to AE0 TPU channel 4 setting PB5DDR Pin function Table below (1) TIOCB4 output 0 PB5 input Modes 4 to 6 B'0000 to B'0101 Table below (2) 1 PB5 output B'0110 to B'1111 A13 Output TIOCB4 input* Operating mode TPU channel 4 setting PB5DDR Pin function Table below (1) TIOCB4 output 0 PB5 input TIOCB4 input* TPU channel 4 setting MD3 to MD0 IOB3 to IOB0 (2) (1) B'0000, B'01xx B'0000 B'0100 B'1xxx CCLR1, CCLR0 Output function Output compare output Other than B'10 PWM mode 2 output B'10 B'0001 to B'0011 B'0101 to B'0111' (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) Mode 7 Table below (2) 1 PB5 output [Legend] x: Don't care Note: * TIOCB4 input when MD3 to MD0=B'0000, B'01xx, and IOB3 to IOB0=B'10xx. Rev. 1.00 Jan. 29, 2008 Page 202 of 666 REJ09B0427-0100 Section 9 I/O Ports * PB4/A12/TIOCA4 The pin function is switched as shown below according to the combination of the operating mode, bits AE3 to AE0 in PFCR, bits MD3 to MD0 in TMDR_4, bits IOA3 to IOB0 in TIOR_4, the TPU channel 4 setting (by bits CCLR1 and CCLR0 in TCR_4), and bit PB4DDR. Operating mode AE3 to AE0 TPU channel 4 setting PB4DDR Pin function Table below (1) TIOCA4 output 0 PB4 input 1 Modes 4 to 6 B'0000 to B'0100 Table below (2) 1 PB4 output B'0101 to B'1111 A12 Output TIOCA4 input* Operating mode TPU channel 4 setting PB4DDR Pin function Table below (1) TIOCA4 output 0 PB4 input Mode 7 Table below (2) 1 PB4 output TIOCA4 input*1 TPU channel 4 setting MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx (2) B'001x (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 Output compare output Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 B'01 PWM mode PWM mode 1 output*2 2 output [Legend] x: Don't care Notes: 1. TIOCA4 input when MD3 to MD0=B'0000, B'01xx, and IOA3 to IOA0=B'10xx. 2. TIOCB4 is disabled. Rev. 1.00 Jan. 29, 2008 Page 203 of 666 REJ09B0427-0100 Section 9 I/O Ports * PB3/A11/TIOCD3 The pin function is switched as shown below according to the combination of the operating mode, bits AE3 to AE0 in PFCR, bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, the TPU channel 3 setting (by bits CCLR2 to CCLR0 in TCR_3), and bit PB3DDR. Operating mode AE3 to AE0 TPU channel 3 setting PB3DDR Pin function Table below (1) TIOCD3 output 0 PB3 input Modes 4 to 6 B'0000 to B'0011 Table below (2) 1 PB3 output B'0100 to B'1111 A11 Output TIOCD3 input* Operating mode TPU channel 3 setting PB3DDR Pin function Table below (1) TIOCD3 output 0 PB3 input TIOCD3 input* TPU channel 3 setting MD3 to MD0 IOD3 to IOD0 B'0000 B'0100 B'1xxx CCLR2 to CCLR0 Output function Output compare output Other than B'110 PWM mode 2 output B'110 (2) B'0000 B'0001 to B'0011 B'0101 to B'0111 (1) (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) Mode 7 Table below (2) 1 PB3 output [Legend] x: Don't care Note: * TIOCD3 input when MD3 to MD0=B'0000, B'01xx, and IOD3 to IOD0=B'10xx. Rev. 1.00 Jan. 29, 2008 Page 204 of 666 REJ09B0427-0100 Section 9 I/O Ports * PB2/A10/TIOCC3 The pin function is switched as shown below according to the combination of the operating mode, bits AE3 to AE0 in PFCR, bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, the TPU channel 3 setting (by bits CCLR2 to CCLR0 in TCR_3), and bit PB2DDR. Operating mode AE3 to AE0 TPU channel 3 setting PB2DDR Pin function Table below (1) TIOCC3 output 0 PB2 input 1 Modes 4 to 6 B'0000 to B'0010 Table below (2) 1 PB2 output B'0011 to B'1111 A10 Output TIOCC3 input* Operating mode TPU channel 3 setting PB2DDR Pin function Table below (1) TIOCC3 output 0 PB2 input Mode 7 Table below (2) 1 PB2 output TIOCC3 input*1 TPU channel 3 setting MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000 B'0100 B'1xxx (1) (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0001 to B'0011 B'0101 to B'0111 Output compare output Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'101 B'101 PWM mode 1 PWM mode 2 output*2 output [Legend] x: Don't care Notes: 1. TIOCC3 input when MD3 to MD0=B'0000 and IOC3 to IOC0=B'10xx. 2. TIOCD3 is disabled. Rev. 1.00 Jan. 29, 2008 Page 205 of 666 REJ09B0427-0100 Section 9 I/O Ports * PB1/A9/TIOCB3 The pin function is switched as shown below according to the combination of the operating mode, bits AE3 to AE0 in PFCR, bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, the TPU channel 3 setting (by bits CCLR2 to CCLR0 in TCR_3), and bit PB1DDR. Operating mode AE3 to AE0 TPU channel 3 setting PB1DDR Pin function Table below (1) TIOCB3 output 0 PB1 input Modes 4 to 6 B'0000 to B'0001 Table below (2) 1 PB1 output B'0010 to B'1111 A9 Output TIOCB3 input* Operating mode TPU channel 3 setting PB1DDR Pin function Table below (1) TIOCB3 output 0 PB1 input TIOCB3 input* TPU channel 3 setting MD3 to MD0 IOB3 to IOB0 (2) (1) B'0000, B'01xx B'0000 B'0100 B'1xxx CCLR1, CCLR0 Output function Output compare output Other than B'010 PWM mode 2 output B'010 B'0001 to B'0011 B'0101 to B'0111 (2) B'0010 B'xx00 (2) (1) B'0011 Other than B'xx00 (2) Mode 7 Table below (2) 1 PB1 output [Legend] x: Don't care Note: * TIOCB3 input when MD3 to MD0=B'0000, B'01xx, and IOB3 to IOB0=B'10xx. Rev. 1.00 Jan. 29, 2008 Page 206 of 666 REJ09B0427-0100 Section 9 I/O Ports * PB0/A8/TIOCA3 The pin function is switched as shown below according to the combination of the operating mode, bits AE3 to AE0 in PFCR, bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, the TPU channel 3 setting (by bits CCLR2 to CCLR0 in TCR_3), and bit PB0DDR. Operating mode AE3 to AE0 TPU channel 3 setting PB0DDR Pin function Table below (1) TIOCA3 output 0 PB0 input 1 Modes 4 to 6 B'0000 Table below (2) 1 PB0 output B'0001 to B'1111 A8 Output TIOCA3 input* Operating mode TPU channel 3 setting PB0DDR Pin function Table below (1) TIOCA3 output 0 PB0 input Mode 7 Table below (2) 1 PB0 output TIOCA3 input*1 TPU channel 3 setting MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx (2) B'001x B'xx00 (1) B'0010 Other than B'xx00 (1) B'0011 (2) B'0000 B'0100 B'1xxx B'0001 to B'0011 B'0101 to B'0111 Output compare output Other than B'xx00 CCLR1, CCLR0 Output function Other than B'001 B'001 PWM mode 1 PWM mode 2 output*2 output [Legend] x: Don't care Notes: 1. TIOCA3 input when MD3 to MD0=B'0000 and IOA3 to IOA0=B'10xx. 2. TIOCB3 is disabled. Rev. 1.00 Jan. 29, 2008 Page 207 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.7 Port C Port C is an 8-bit I/O port. Port C also functions as address bus output pins. The pin functions are determined by the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. * * * * * Port C data direction register (PCDDR) Port C data register (PCDR) Port C register (PORTC) Port C pull-up MOS control register (PCPCR) Port C open-drain control register (PCODR) Port C Data Direction Register (PCDDR) 9.7.1 PCDDR is a write-only register, the individual bits of which specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description In modes 4 and 5, regardless of the PCDDR setting, the corresponding port C pin is an output pin. In mode 6, setting a PCDDR bit to 1 makes the corresponding port C pin an address output pin, while clearing the bit to 0 makes the pin an input pin. In mode 7, setting a PCDDR bit to 1 makes the corresponding port C pin an output pin, while clearing the bit to 0 makes the pin an input pin. Rev. 1.00 Jan. 29, 2008 Page 208 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.7.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit 7 6 5 4 3 2 1 0 Bit Name PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description An output data for a pin is stored when the pin function is specified to a general purpose output port. 9.7.3 Port C Register (PORTC) PORTC shows the pin states. It cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Initial Value * * * * * * * * R/W R R R R R R R R Description If this register read is performed while PCDDR bits are set to 1, the PCDR values are read. If this register read is performed while PCDDR bits are cleared to 0, the pin states are read. Determined by state of pins PC7 to PC0. Rev. 1.00 Jan. 29, 2008 Page 209 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.7.4 Port C Pull-Up MOS Control Register (PCPCR) PCPCR controls the MOS input pull-up function incorporated into port C on an individual bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR and in PCDDR, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin. In mode 7, if a pin is in the input state in accordance with the settings in PCDDR, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin. 9.7.5 Port C Open-Drain Control Register (PCODR) PCODR controls output of port C. Bit 7 6 5 4 3 2 1 0 Bit Name PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description If PCODR is set to 1 by setting AE3 to AE0 in PFCR in mode other than address output mode, port C pins function as NMOS open drain outputs and when the setting is cleared to 0, the pins function as CMOS outputs. Rev. 1.00 Jan. 29, 2008 Page 210 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.7.6 Pin Functions The correspondence between the register specification and the pin functions is shown below. * PC7/A7 to PC0/A0 The pin function is switched as shown below according to the combination of the operating mode, the AE3 to AE0 bits in PFCR, and the PCnDDR bit in PCDDR. Operating Mode Setting of Address output AE3 to AE0 enabled PCnDDR Pin function A7 to A0 output Modes 4 and 6 Address output disabled 0 PC7 to PC0 input 1 PC7 to PC0 output 0 Mode 7 1 PC7 to PC0 output PC7 to PC0 input Rev. 1.00 Jan. 29, 2008 Page 211 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.8 Port D Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. * * * * Port D data direction register (PDDDR) Port D data register (PDDR) Port D register (PORTD) Port D pull-up MOS control register (PDPCR) Port D Data Direction Register (PDDDR) 9.8.1 PDDDR is a write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PDDDR bit to 1 makes the corresponding port D pin an output pin, while clearing the bit to 0 makes the pin an input pin. Rev. 1.00 Jan. 29, 2008 Page 212 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.8.2 Port D Data Register (PDDR) PDDR stores output data for the port D pins. Bit 7 6 5 4 3 2 1 0 Bit Name PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description An output data for a pin is stored when the pin function is specified to a general purpose output port. 9.8.3 Port D Register (PORTD) PORTD shows the pin states. It cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Initial Value * * * * * * * * R/W R R R R R R R R Description If this register read is performed while PDDDR bits are set to 1, the PDDR values are read. If this register read is performed while PDDDR bits are cleared to 0, the pin states are read. Determined by state of pins PD7 to PD0. Rev. 1.00 Jan. 29, 2008 Page 213 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.8.4 Port D Pull-Up MOS Control Register (PDPCR) PDPCR controls the MOS input pull-up function incorporated into port D on an individual bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description In mode 7, if a pin is in the input state in accordance with the setting in PDDDR, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. 9.8.5 Pin Functions The correspondence between the register specification and the pin functions is shown below. Operating Mode PDnDDR Pin function (n = 7 to 0) Mode 4 to 6 D15 to D8 I/O 0 PD7 to PD0 input Mode 7 1 PD7 to PD0 output Rev. 1.00 Jan. 29, 2008 Page 214 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.9 Port E Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software. * * * * Port E data direction register (PEDDR) Port E data register (PEDR) Port E register (PORTE) Port E pull-up MOS control register (PEPCR) Port E Data Direction Register (PEDDR) 9.9.1 PEDDR is a write-only register, the individual bits of which specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PEDDR bit to 1 makes the corresponding port E pin an output pin, while clearing the bit to 0 makes the pin an input pin. Rev. 1.00 Jan. 29, 2008 Page 215 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.9.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit 7 6 5 4 3 2 1 0 Bit Name PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description An output data for a pin is stored when the pin function is specified to a general purpose output port. 9.9.3 Port E Register (PORTE) PORTE shows the pin states. It cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Initial Value * * * * * * * * R/W R R R R R R R R Description If this register read is performed while PEDDR bits are set to 1, the PEDR values are read. Determined by state of pins PE7 to PE0. Rev. 1.00 Jan. 29, 2008 Page 216 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.9.4 Port E Pull-Up MOS Control Register (PEPCR) PEPCR controls the MOS input pull-up function incorporated into port E on an individual bit basis. Bit 7 6 5 4 3 2 1 0 Bit Name PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description In modes 4 to 6 with 8-bit-bus mode selected, or in mode 7, if a pin is in the input state in accordance with the setting in PEDDR, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin. (n = 7 to 0) 9.9.5 Pin Functions The correspondence between the register specification and the pin functions is shown below. Operating Mode Bus width setting PEnDDR Pin function (n = 7 to 0) 16-bit mode -- D7 to D0 I/O 0 PE7 to PE0 input Modes 4 to 6 8-bit mode 1 PE7 to PE0 output 0 PE7 to PE0 input Mode 7 -- 1 PE7 to PE0 output Rev. 1.00 Jan. 29, 2008 Page 217 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.10 Port F Port F is a 6-bit I/O port. Port F also functions as external interrupt input pins, the A/D trigger input pin, bus control signal I/O pins, and as the system clock output pin. * Port F data direction register (PFDDR) * Port F data register (PFDR) * Port F register (PORTF) 9.10.1 Port F Data Direction Register (PFDDR) PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. Bit 7 Bit Name PF7DDR Initial Value 1* R/W W Description Setting a PFDDR bit to 1 makes the PF7 pin a output pin, while clearing the bit to 0 makes the pin an input pin. Setting a PFDDR bit to 1 makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port. Bit 2 and bit 1 are reserved bits. 6 5 4 3 2 1 0 Note: * PF6DDR PF5DDR PF4DDR PF3DDR PF0DDR 0 0 0 0 W W W W Undefined Undefined 0 W Reserved Reserved The initial value is 0 in mode 7. Rev. 1.00 Jan. 29, 2008 Page 218 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.10.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit 7 6 5 4 3 2 1 0 Bit Name PF7DR PF6DR PF5DR PF4DR PF3DR PF0DR Initial Value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Reserved Reserved Description An output data for a pin is stored when the pin function is specified to a general purpose output port. Bit 2 and bit 1 are reserved bits. Undefined Undefined 0 R/W 9.10.3 Port F Register (PORTF) PORTF shows the pin states. It cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Initial Value Undefined * Undefined * Undefined * Undefined * Undefined * Undefined * Undefined * Undefined * R/ W R R R R R R R R Description If this register read is performed while PFDDR bits are set to 1, the PFDR values are read. If this register read is performed while PFDDR bits are cleared to 0, the pin states are read. Determined by state of pins PF7 to PF0. Rev. 1.00 Jan. 29, 2008 Page 219 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.10.4 Pin Functions The correspondence between the register specification and the pin functions is shown below. * PF7/ The pin function is switched as shown below according to bit PF7DDR. PF7DDR Pin function 0 PF7 input 1 output * PF6/AS The pin function is switched as shown below according to the operating mode and the setting of PF6DDR bit. Operating Mode PF6DDR Pin function Modes 4 to 6 AS output 0 PF6 input Mode 7 1 PF6 output * PF5/RD The pin function is switched as shown below according to the operating mode and the setting of PF5DDR bit. Operating Mode PF5DDR Pin function Modes 4 to 6 RD output 0 PF5 input Mode 7 1 PF5 output * PF4/HWR The pin function is switched as shown below according to the operating mode and the setting of PF4DDR bit. Operating Mode PF4DDR Pin function Modes 4 to 6 HWR output 0 PF4 input Mode 7 1 PF4 output Rev. 1.00 Jan. 29, 2008 Page 220 of 666 REJ09B0427-0100 Section 9 I/O Ports * PF3/LWR/ADTRG/IRQ3 The pin function is switched as shown below according to the operating mode and the setting of bits TRGS1 and TRGS0 bits in ADCR and PF3DDR bit. Operating Mode Bus Mode PF3DDR Pin function 16 LWR output 0 PF3 input Modes 4 to 6 8 1 PF3 output 0 PF3 input Mode 7 1 PF3 output ADTRG input*1 IRQ3 input*2 Notes: 1 2 ADTRG input when TRGS0=TRGS1=1. When using as the external interrupt pins, refrain from using as I/O pins of other functions. * PF0/IRQ2 The pin function is switched as shown below according to the PF0DDR bit. PF0DDR Pin function 0 PF0 input IRQ2 input 1 PF0 output Rev. 1.00 Jan. 29, 2008 Page 221 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.11 Port H Port H is an 8-bit I/O port. Port H pins also function as motor control PWM timer output pins. * Port H data direction register (PHDDR) * Port H data register (PHDR) * Port H register (PORTH) 9.11.1 Port H Data Direction Register (PHDDR) PHDDR is a write-only register, the individual bits of which specify input or output for the pins of port H. PHDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PHDDR bit to 1 makes the corresponding port H pin an output pin, while clearing the bit to 0 makes the pin an input pin. Rev. 1.00 Jan. 29, 2008 Page 222 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.11.2 Port H Data Register (PHDR) PHDR stores output data for the port H pins. Bit 7 6 5 4 3 2 1 0 Bit Name PH7DR PH6DR PH5DR PH4DR PH3DR PH2DR PH1DR PH0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description An output data for a pin is stored when the pin function is specified to a general purpose output port. 9.11.3 Port H Register (PORTH) PORTH shows the pin states. It cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 Initial Value * * * * * * * * R/W R R R R R R R R Description If this register read is performed while PHDDR bits are set to 1, the PHDR values are read. If this register read is performed while PHDDR bits are cleared to 0, the pin states are read. Determined by state of pins PH7 to PH0. Rev. 1.00 Jan. 29, 2008 Page 223 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.11.4 Pin Functions The correspondence between the register specification and the pin functions is shown below. The pin function is switched as shown below according to the OE1A to OE1H bits in PWOCR_1 of the motor control PWM timer and the PHDDR values. OE1A to OE1H PHDDR Pin function 1 Motor control PWM timer output 0 PH7 to PH0 input 0 1 PH7 to PH0 output Rev. 1.00 Jan. 29, 2008 Page 224 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.12 Port J Port J is an 8-bit I/O port. Port J pins also function as motor control PWM timer output pins. * Port J data direction register (PJDDR) * Port J data register (PJDR) * Port J register (PORTJ) 9.12.1 Port J Data Direction Register (PJDDR) PJDDR is a write-only register, the individual bits of which specify input or output for the pins of port J. PJDDR cannot be read; if it is, an undefined value will be read. Bit 7 6 5 4 3 2 1 0 Bit Name PJ7DDR PJ6DDR PJ5DDR PJ4DDR PJ3DDR PJ2DDR PJ1DDR PJ0DDR Initial Value 0 0 0 0 0 0 0 0 R/W W W W W W W W W Description Setting a PJDDR bit to 1 makes the corresponding port J pin an output pin, while clearing the bit to 0 makes the pin an input pin. Rev. 1.00 Jan. 29, 2008 Page 225 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.12.2 Port J Data Register (PJDR) PJDR stores output data for the port J pins. Bit 7 6 5 4 3 2 1 0 Bit Name PJ7DR PJ6DR PJ5DR PJ4DR PJ3DR PJ2DR PJ1DR PJ0DR Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description An output data for a pin is stored when the pin function is specified to a general purpose output port. 9.12.3 Port J Register (PORTJ) PORTJ shows the pin states. It cannot be modified. Bit 7 6 5 4 3 2 1 0 Note: * Bit Name PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 Initial Value * * * * * * * * R/W R R R R R R R R Description If this register read is performed while PJDDR bits are set to 1, the PJDR values are read. If this register read is performed while PJDDR bits are cleared to 0, the pin states are read. Determined by state of pins PJ7 to PJ0. Rev. 1.00 Jan. 29, 2008 Page 226 of 666 REJ09B0427-0100 Section 9 I/O Ports 9.12.4 Pin Functions The correspondence between the register specification and the pin functions is shown below. The pin function is switched as shown below according to the OE2A to OE2H bits in PWOCR_2 of the motor control PWM timer and the PJDDR values. OE2A to OE2H PJDDR Pin function 1 Motor control PWM timer output 0 PJ7 to PJ0 input 0 1 PJ7 to PJ0 output Rev. 1.00 Jan. 29, 2008 Page 227 of 666 REJ09B0427-0100 Section 9 I/O Ports Rev. 1.00 Jan. 29, 2008 Page 228 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) comprised of six 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure 10.1, respectively. 10.1 Features * Maximum 16-pulse input/output * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input/output is possible by synchronous counter operation A maximum 15-phase PWM output is possible in combination with synchronous operation * Buffer operation settable for channels 0 and 3 * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 * Cascaded operation * Fast access via internal 16-bit bus * 26 interrupt sources * Automatic transfer of register data * Programmable pulse generator (PPG) output trigger can be generated * A/D converter conversion start trigger can be generated * Module stop mode can be set Rev. 1.00 Jan. 29, 2008 Page 229 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 TPU Functions Item Count clock Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 /1 /4 /16 /64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TGR compare match or input capture /1 /4 /16 /64 /256 TCLKA TCLKB TGRA_1 TGRB_1 TIOCA1 TIOCB1 /1 /4 /16 /64 /1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 TIOCA2 TIOCB2 /1 /4 /16 /64 /256 /1024 /4096 TCLKA TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture /1 /4 /16 /64 /1024 TCLKA TCLKC TGRA_4 TGRB_4 TIOCA4 TIOCB4 /1 /4 /16 /64 /256 TCLKA TCLKC TCLKD TGRA_5 TGRB_5 TIOCA5 TIOCB5 General registers (TGR) General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation Rev. 1.00 Jan. 29, 2008 Page 230 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 TGR compare match or input capture TGRA_1 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture Channel 2 TGR compare match or input capture TGRA_2 compare match or input capture TGRA_2/ TGRB_2 compare match or input capture Channel 3 TGR compare match or input capture TGRA_3 compare match or input capture TGRA_3/ TGRB_3 compare match or input capture Channel 4 TGR compare match or input capture TGRA_4 compare match or input capture Channel 5 TGR compare match or input capture TGRA_5 compare match or input capture DTC TGR activation compare match or input capture A/D TGRA_0 converter compare trigger match or input capture PPG trigger TGRA_0/ TGRB_0 compare match or input capture Rev. 1.00 Jan. 29, 2008 Page 231 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Item Interrupt sources Channel 0 5 sources * Channel 1 4 sources Channel 2 4 sources Channel 3 5 sources Channel 4 4 sources Channel 5 4 sources Compare match or input capture 5A Compare match or input capture 5B Overflow Underflow Compare * match or input capture 0A Compare * match or input capture 0B Compare * match or * input capture 0C Compare match or input capture 0D Overflow Compare * match or input capture 1A Compare * match or input capture 1B Overflow * Underflow * Compare * match or input capture 2A Compare * match or input capture 2B Overflow Underflow * Compare * match or input capture 3A Compare * match or input capture 3B Compare * match or * input capture 3C Compare match or input capture 3D Overflow Compare * match or input capture 4A Compare * match or input capture 4B Overflow * Underflow * * * * * * * [Legend] Possible : : Not possible Rev. 1.00 Jan. 29, 2008 Page 232 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) TIORH TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Input/output pins Channel 3: TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Control logic for channels 3 to 5 TIOR Channel 5: TMDR Channel 5 TSR TIER TCR Channel 4: TIOR Clock input Internal clock: /1 /4 /16 /64 /256 /1024 /4096 TCLKA TCLKB TCLKC TCLKD TIER TCR Module data bus TSYR TGRA TGRB TCNT Interrupt request signals Channel 3: TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 Channel 4: TGIA_4 TGIB_4 TCIV_4 TCIU_4 Channel 5: TGIA_5 TGIB_5 TCIV_5 TCIU_5 TMDR Channel 4 TSR TIER TCR TGRA TGRB TCNT Control logic Internal data bus Bus interface Common External clock: TSTR A/D converter conversion start signal PPG output trigger signal TMDR Channel 2 TSR TGRA TIOR Input/output pins Channel 0: TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIER TCR TGRB TCNT Channel 2: TIORH TIORL TMDR Channel 0 TSR TIER TCR Channel 1: Interrupt request signals Channel 3: TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 Channel 4: TGIA_1 TGIB_1 TCIV_1 TCIU_1 Channel 5: TGIA_2 TGIB_2 TCIV_2 TCIU_2 TMDR Control logic for channel 0 to 2 Channel 1 TSR TIOR TGRA TGRB TGRC TGRD TGRB TCNT TCNT [Legend] TSTR: TSYR: TCR: TMDR: Timer start register Timer synchro register Timer control register Timer mode register TIOR (H, L): TIER: TSR: TGR (A, B, C, D): Timer I/O control registers (H, L) Timer interrupt enable register Timer status register TImer general registers (A, B, C, D) Figure 10.1 Block Diagram of TPU TIER TCR TGRA Rev. 1.00 Jan. 29, 2008 Page 233 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.2 Input/Output Pins Table 10.2 TPU Pins Channel All Symbol TCLKA TCLKB TCLKC TCLKD 0 TIOCA0 TIOCB0 TIOCC0 TIOCD0 1 TIOCA1 TIOCB1 2 TIOCA2 TIOCB2 3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 4 TIOCA4 TIOCB4 5 TIOCA5 TIOCB5 I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function External clock A input pin (Channel 1 and 5 phase counting mode A phase input) External clock B input pin (Channel 1 and 5 phase counting mode B phase input) External clock C input pin (Channel 2 and 4 phase counting mode A phase input) External clock D input pin (Channel 2 and 4 phase counting mode B phase input) TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRA_5 input capture input/output compare output/PWM output pin TGRB_5 input capture input/output compare output/PWM output pin Rev. 1.00 Jan. 29, 2008 Page 234 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3 Register Descriptions The TPU has the following registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Timer control register_0 (TCR_0) Timer mode register_0 (TMDR_0) Timer I/O control register H_0 (TIORH_0) Timer I/O control register L_0 (TIORL_0) Timer interrupt enable register_0 (TIER_0) Timer status register_0 (TSR_0) Timer counter_0 (TCNT_0) Timer general register A_0 (TGRA_0) Timer general register B_0 (TGRB_0) Timer general register C_0 (TGRC_0) Timer general register D_0 (TGRD_0) Timer control register_1 (TCR_1) Timer mode register_1 (TMDR_1) Timer I/O control register _1 (TIOR_1) Timer interrupt enable register_1 (TIER_1) Timer status register_1 (TSR_1) Timer counter_1 (TCNT_1) Timer general register A_1 (TGRA_1) Timer general register B_1 (TGRB_1) Timer control register_2 (TCR_2) Timer mode register_2 (TMDR_2) Timer I/O control register_2 (TIOR_2) Timer interrupt enable register_2 (TIER_2) Timer status register_2 (TSR_2) Timer counter_2 (TCNT_2) Timer general register A_2 (TGRA_2) Timer general register B_2 (TGRB_2) Timer control register_3 (TCR_3) Timer mode register_3 (TMDR_3) Rev. 1.00 Jan. 29, 2008 Page 235 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) * * * * * * * * * * * * * * * * * * * * * * * * * Timer I/O control register H_3 (TIORH_3) Timer I/O control register L_3 (TIORL_3) Timer interrupt enable register_3 (TIER_3) Timer status register_3 (TSR_3) Timer counter_3 (TCNT_3) Timer general register A_3 (TGRA_3) Timer general register B_3 (TGRB_3) Timer general register C_3 (TGRC_3) Timer general register D_3 (TGRD_3) Timer control register_4 (TCR_4) Timer mode register_4 (TMDR_4) Timer I/O control register _4 (TIOR_4) Timer interrupt enable register_4 (TIER_4) Timer status register_4 (TSR_4) Timer counter_4 (TCNT_4) Timer general register A_4 (TGRA_4) Timer general register B_4 (TGRB_4) Timer control register_5 (TCR_5) Timer mode register_5 (TMDR_5) Timer I/O control register_5 (TIOR_5) Timer interrupt enable register_5 (TIER_5) Timer status register_5 (TSR_5) Timer counter_5 (TCNT_5) Timer general register A_5 (TGRA_5) Timer general register B_5 (TGRB_5) Common Registers * Timer start register (TSTR) * Timer synchro register (TSYR) Rev. 1.00 Jan. 29, 2008 Page 236 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel (channel 0 to 5). TCR register settings should be conducted only when TCNT operation is stopped. Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 0 to 2 These bits select the TCNT counter clearing source. See tables 10.3 and 10.4 for details. Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is /4 or slower. This setting is ignored if the input clock is /1, or when overflow/underflow of another channel is selected. 00: Count at rising edge 01: Count at falling edge 1X: Count at both edges [Legend] X: Don't care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 10.5 to 10.10 for details. Rev. 1.00 Jan. 29, 2008 Page 237 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.3 CCLR0 to CCLR2 (Channels 0 and 3) Bit 7 Channel CCLR2 0, 3 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 1 0 0 1 1 0 1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 10.4 CCLR0 to CCLR2 (Channels 1, 2, 4, and 5) Bit 7 Bit 6 Channel Reserved*2 CCLR1 1, 2, 4, 5 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1 Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified. Rev. 1.00 Jan. 29, 2008 Page 238 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.5 TPSC0 to TPSC2 (Channel 0) Bit 2 Channel TPSC2 0 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Table 10.6 TPSC0 to TPSC2 (Channel 1) Bit 2 Channel TPSC2 1 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on /256 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Rev. 1.00 Jan. 29, 2008 Page 239 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.7 TPSC0 to TPSC2 (Channel 2) Bit 2 Channel TPSC2 2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 10.8 TPSC0 to TPSC2 (Channel 3) Bit 2 Channel TPSC2 3 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input Internal clock: counts on /1024 Internal clock: counts on /256 Internal clock: counts on /4096 Rev. 1.00 Jan. 29, 2008 Page 240 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.9 TPSC0 to TPSC2 (Channel 4) Bit 2 Channel TPSC2 4 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /1024 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Table 10.10 TPSC0 to TPSC2 (Channel 5) Bit 2 Channel TPSC2 5 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Description Internal clock: counts on /1 Internal clock: counts on /4 Internal clock: counts on /16 Internal clock: counts on /64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on /256 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Rev. 1.00 Jan. 29, 2008 Page 241 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be changed only when TCNT operation is stopped. Bit 7, 6 Bit Name Initial value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 5 BFB 0 R/W Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 0 to 3 These bits are used to set the timer operating mode. MD3 is a reserved bit. In a write, it should always be written with 0. See table 10.11 for details. Rev. 1.00 Jan. 29, 2008 Page 242 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.11 MD0 to MD3 Bit 3 1 MD3* 0 Bit 2 MD2*2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 1 X X X Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 [Legend] X: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. Rev. 1.00 Jan. 29, 2008 Page 243 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. * TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit 7 6 5 4 3 2 1 0 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description I/O Control B0 to B3 Specify the function of TGRB. I/O Control A0 to A3 Specify the function of TGRA. * TIORL_0, TIORL_3 Bit 7 6 5 4 3 2 1 0 Bit Name IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description I/O Control D0 to D3 Specify the function of TGRD. I/O Control C0 to C3 Specify the function of TGRC. Rev. 1.00 Jan. 29, 2008 Page 244 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.12 TIORH_0 (Channel 0) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRB_0 Function Output compare register TIOCB0 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCB0 pin register Input capture at rising edge Capture input source is the TIOCB0 pin Input capture at falling edge Capture input source is the TIOCB0 pin Input capture at both edges. Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* [Legend] X: Don't care Note: * When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. Rev. 1.00 Jan. 29, 2008 Page 245 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.13 TIORL_0 (Channel 0) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRD_0 Function Output compare register*2 TIOCD0 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCD0 pin register*2 Input capture at rising edge Capture input source is the TIOCD0 pin Input capture at falling edge Capture input source is the TIOCD0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down* 1 [Legend] X: Don't care Notes: 1. When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and /1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Jan. 29, 2008 Page 246 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.14 TIOR_1 (Channel 1) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCB1 pin register Input capture at rising edge Capture input source is the TIOCB1 pin Input capture at falling edge Capture input source is the TIOCB1 pin Input capture at both edges TGRC_0 compare match/ input capture Input capture at generation of TGRC_0 compare match/input capture [Legend] X: Don't care Rev. 1.00 Jan. 29, 2008 Page 247 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.15 TIOR_2 (Channel 2) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 [Legend] X: Don't care X TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCB2 pin register Input capture at rising edge Capture input source is the TIOCB2 pin Input capture at falling edge Capture input source is the TIOCB2 pin Input capture at both edges Rev. 1.00 Jan. 29, 2008 Page 248 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.16 TIORH_3 (Channel 3) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRB_3 Function Output compare register TIOCB3 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCB3 pin register Input capture at rising edge Capture input source is the TIOCB3 pin Input capture at falling edge Capture input source is the TIOCB3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* [Legend] X: Don't care Note: * When bits TPSC0 to TPSC2 in TCR_4 are set to B000 and /1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. Rev. 1.00 Jan. 29, 2008 Page 249 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.17 TIORL_3 (Channel 3) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRD_3 Function Output compare register*2 TIOCD3 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCD3 pin register*2 Input capture at rising edge Capture input source is the TIOCD3 pin Input capture at falling edge Capture input source is the TIOCD3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down* 1 [Legend] X: Don't care Notes: 1. When bits TPSC0 to TPSC2 in TCR_4 are set to B'000 and /1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Jan. 29, 2008 Page 250 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.18 TIOR_4 (Channel 4) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRB_4 Function Output compare register TIOCB4 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCB4 pin register Input capture at rising edge Capture input source is the TIOCB4 pin Input capture at falling edge Capture input source is the TIOCB4 pin Input capture at both edges Capture input source is TGRC_3 compare match/input capture Input capture at generation of TGRC_3 compare match/input capture [Legend] X: Don't care Rev. 1.00 Jan. 29, 2008 Page 251 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.19 TIOR_5 (Channel 5) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 [Legend] X: Don't care X TGRB_5 Function Output compare register TIOCB5 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCB5 pin register Input capture at rising edge Capture input source is the TIOCB5 pin Input capture at falling edge Capture input source is the TIOCB5 pin Input capture at both edges Rev. 1.00 Jan. 29, 2008 Page 252 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.20 TIORH_0 (Channel 0) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRA_0 Function Output compare register TIOCA0 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCA0 pin register Input capture at rising edge Capture input source is the TIOCA0 pin Input capture at falling edge Capture input source is the TIOCA0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Rev. 1.00 Jan. 29, 2008 Page 253 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.21 TIORL_0 (Channel 0) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRC_0 Function Output compare register* TIOCC0 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCC0 pin register* Input capture at rising edge Capture input source is the TIOCC0 pin Input capture at falling edge Capture input source is the TIOCC0 pin Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down [Legend] X: Don't care Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Jan. 29, 2008 Page 254 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.22 TIOR_1 (Channel 1) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRA_1 Function Output compare register TIOCA1 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCA1 pin register Input capture at rising edge Capture input source is the TIOCA1 pin Input capture at falling edge Capture input source is the TIOCA1 pin Input capture at both edges Capture input source is TGRA_0 compare match/input capture Input capture at generation of channel 0/TGRA_0 compare match/input capture [Legend] X: Don't care Rev. 1.00 Jan. 29, 2008 Page 255 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.23 TIOR_2 (Channel 2) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 [Legend] X: Don't care X TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCA2 pin register Input capture at rising edge Capture input source is the TIOCA2 pin Input capture at falling edge Capture input source is the TIOCA2 pin Input capture at both edges Rev. 1.00 Jan. 29, 2008 Page 256 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.24 TIORH_3 (Channel 3) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRA_3 Function Output compare register TIOCA3 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCA3 pin register Input capture at rising edge Capture input source is the TIOCA3 pin Input capture at falling edge Capture input source is the TIOCA3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down [Legend] X: Don't care Rev. 1.00 Jan. 29, 2008 Page 257 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.25 TIORL_3 (Channel 3) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRC_3 Function Output compare register* TIOCC3 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCC3 pin register* Input capture at rising edge Capture input source is the TIOCC3 pin Input capture at falling edge Capture input source is the TIOCC3 pin Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT_4 count-up/count-down [Legend] X: Don't care Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 1.00 Jan. 29, 2008 Page 258 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.26 TIOR_4 (Channel 4) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X TGRA_4 Function Output compare register TIOCA4 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCA4 pin register Input capture at rising edge Capture input source is the TIOCA4 pin Input capture at falling edge Capture input source is the TIOCA4 pin Input capture at both edges Capture input source is TGRA_3 compare match/input capture Input capture at generation of TGRA_3 compare match/input capture [Legend] X: Don't care Rev. 1.00 Jan. 29, 2008 Page 259 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.27 TIOR_5 (Channel 5) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 [Legend] X: Don't care X TGRA_5 Function Output compare register TIOCA5 Pin Function Output disabled Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output disabled Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture Capture input source is the TIOCA5 pin register Input capture at rising edge Capture input source is the TIOCA5 pin Input capture at falling edge Capture input source is the TIOCA5 pin Input capture at both edges Rev. 1.00 Jan. 29, 2008 Page 260 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.4 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit 7 Bit Name TTGE Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 5 TCIEU 1 0 R/W Reserved This bit is always read as 1 and cannot be modified. Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled Rev. 1.00 Jan. 29, 2008 Page 261 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 2 Bit Name TGIEC Initial value 0 R/W R/W Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev. 1.00 Jan. 29, 2008 Page 262 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.5 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down 1: TCNT counts up 6 5 TCFU 1 0 R/(W) Reserved This bit is always read as 1 and cannot be modified. Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 4 TCFV 0 R/(W) Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 Rev. 1.00 Jan. 29, 2008 Page 263 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit Name TGFD Initial value 0 R/W R/(W) Description Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. Only 0 can be written, for flag clearing. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRD and TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register When DTC is activated by TGID interrupt and the DISEL bit of MRB in DTC is 0 When 0 is written to TGFD after reading TGFD = 1 [Clearing conditions] * * 2 TGFC 0 R/(W) Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. Only 0 can be written, for flag clearing. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRC and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register When DTC is activated by TGIC interrupt and the DISEL bit of MRB in DTC is 0 When 0 is written to TGFC after reading TGFC = 1 [Clearing conditions] * * Rev. 1.00 Jan. 29, 2008 Page 264 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Bit 1 Bit Name TGFB Initial value 0 R/W R/(W) Description Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * * When TCNT = TGRB and TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register When DTC is activated by TGIB interrupt and the DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB = 1 [Clearing conditions] * * 0 TGFA 0 R/(W) Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * * When TCNT = TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register When DTC is activated by TGIA interrupt and the DISEL bit of MRB in DTC is 0 When 0 is written to TGFA after reading TGFA = 1 [Clearing conditions] * * Rev. 1.00 Jan. 29, 2008 Page 265 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 10.3.7 Timer General Register (TGR) The TGR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRATGRC and TGRBTGRD. 10.3.8 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit 7, 6 5 4 3 2 1 0 Bit Name CST5 CST4 CST3 CST2 CST1 CST0 Initial value All 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W Description Reserved The write value should always be 0. Counter Start 0 to 5 (CST0 to CST5) These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_0 to TCNT_5 count operation is stopped 1: TCNT_0 to TCNT_5 performs count operation Rev. 1.00 Jan. 29, 2008 Page 266 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.9 Timer Synchro Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 5 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit 7, 6 5 4 3 2 1 0 Bit Name SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value All 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved The write value should always be 0. Timer Synchro 0 to 5 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_0 to TCNT_5 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_0 to TCNT_5 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible Rev. 1.00 Jan. 29, 2008 Page 267 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4 10.4.1 Operation Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. 1. Example of count operation setting procedure Figure 10.2 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. [5] Set the CST bit in TSTR to 1 to start the counter operation. Operation selection Select counter clock [1] Periodic counter Free-running counter Select counter clearing source [2] [3] Select output compare register Set period [4] Start count operation [5] Start count operation Figure 10.2 Example of Counter Operation Setting Procedure Rev. 1.00 Jan. 29, 2008 Page 268 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10.3 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10.3 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 10.4 illustrates periodic counter operation. Rev. 1.00 Jan. 29, 2008 Page 269 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 10.4 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. Example of setting procedure for waveform output by compare match Figure 10.5 shows an example of the setting procedure for waveform output by compare match [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin unit the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation. Output selection Select waveform output mode [1] Set output timing [2] Start count operation [3] Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match Rev. 1.00 Jan. 29, 2008 Page 270 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 2. Examples of waveform output operation Figure 10.6 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time Figure 10.6 Example of 0 Output/1 Output Operation Figure 10.7 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output TIOCB TIOCA Figure 10.7 Example of Toggle Output Operation Rev. 1.00 Jan. 29, 2008 Page 271 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, /1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if /1 is selected. 1. Example of input capture operation setting procedure Figure 10.8 shows an example of the input capture operation setting procedure. [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. [1] Input selection Select input capture input Start count [2] Figure 10.8 Example of Input Capture Operation Setting Procedure Rev. 1.00 Jan. 29, 2008 Page 272 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 2. Example of input capture operation Figure 10.9 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Counter cleared by TIOCB input (falling edge) TCNT value H'0180 H'0160 H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10.9 Example of Input Capture Operation Rev. 1.00 Jan. 29, 2008 Page 273 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 10.10 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source Start count No [3] Set synchronous counter clearing Start count [4] [4] [5] [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 10.10 Example of Synchronous Operation Setting Procedure Rev. 1.00 Jan. 29, 2008 Page 274 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation: Figure 10.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 10.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time TIOCA_0 TIOCA_1 TIOCA_2 Figure 10.11 Example of Synchronous Operation Rev. 1.00 Jan. 29, 2008 Page 275 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10.28 shows the register combinations used in buffer operation. Table 10.28 Register Combinations in Buffer Operation Channel 0 Timer General Register TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.12. Compare match signal Buffer register Timer general register Comparator TCNT Figure 10.12 Compare Match Buffer Operation * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10.13. Rev. 1.00 Jan. 29, 2008 Page 276 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Input capture signal Buffer register Timer general register TCNT Figure 10.13 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 10.14 shows an example of the buffer operation setting procedure. Buffer operation Select TGR function [1] [1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. Set buffer operation [2] Start count [3] Figure 10.14 Example of Buffer Operation Setting Procedure Examples of Buffer Operation: 1. When TGR is an output compare register Figure 10.15 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 10.4.5, PWM Modes. Rev. 1.00 Jan. 29, 2008 Page 277 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 10.15 Example of Buffer Operation (1) 2. When TGR is an input capture register Figure 10.16 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. Rev. 1.00 Jan. 29, 2008 Page 278 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 10.16 Example of Buffer Operation (2) Rev. 1.00 Jan. 29, 2008 Page 279 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10.29 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 10.29 Cascaded Combinations Combination Channels 1 and 2 Channels 4 and 5 Upper 16 Bits TCNT_1 TCNT_4 Lower 16 Bits TCNT_2 TCNT_5 Example of Cascaded Operation Setting Procedure: Figure 10.17 shows an example of the setting procedure for cascaded operation. Cascaded operation Set cascading [1] [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Start count [2] Figure 10.17 Cascaded Operation Setting Procedure Examples of Cascaded Operation: Figure 10.18 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1, when TGRA_1 and TGRA_2 have been designated as input capture registers, and when TIOC pin rising edge has been selected. Rev. 1.00 Jan. 29, 2008 Page 280 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2. TCNT_1 clock TCNT_1 TCNT_2 clock TCNT_2 TIOCA1, TIOCA2 TGRA_1 H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2 TGRA_2 H'0000 Figure 10.18 Example of Cascaded Operation (1) Figure 10.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKA TCLKB TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 10.19 Example of Cascaded Operation (2) Rev. 1.00 Jan. 29, 2008 Page 281 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty cycle. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 10.30. Rev. 1.00 Jan. 29, 2008 Page 282 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.30 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGR4A_4 TGR4B_4 5 Note: * TGRA_5 TGRB_5 TIOCA5 TIOCA4 TIOCC3 TIOCA3 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Rev. 1.00 Jan. 29, 2008 Page 283 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 10.20 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level [3] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 start the count operation. Set TGR [4] Set PWM mode [5] Start count [6] Figure 10.20 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 10.21 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty cycle levels. Rev. 1.00 Jan. 29, 2008 Page 284 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 10.21 Example of PWM Mode Operation (1) Figure 10.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty cycle levels. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 10.22 Example of PWM Mode Operation (2) Rev. 1.00 Jan. 29, 2008 Page 285 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB rewritten TGRA TGRB H'0000 TGRB rewritten TGRB rewritten Time TIOCA 0% duty Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty 0% duty TGRB rewritten Time TIOCA Figure 10.23 Example of PWM Mode Operation (3) Rev. 1.00 Jan. 29, 2008 Page 286 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 10.31 shows the correspondence between external clock pins and channels. Table 10.31 Phase Counting Mode Clock Input Pins External Clock Pins Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD Example of Phase Counting Mode Setting Procedure: Figure 10.24 shows an example of the phase counting mode setting procedure. Phase counting mode [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. [1] Select phase counting mode Start count [2] Figure 10.24 Example of Phase Counting Mode Setting Procedure Rev. 1.00 Jan. 29, 2008 Page 287 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 10.25 shows an example of phase counting mode 1 operation, and table 10.32 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.25 Example of Phase Counting Mode 1 Operation Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count Rev. 1.00 Jan. 29, 2008 Page 288 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 2. Phase counting mode 2 Figure 10.26 shows an example of phase counting mode 2 operation, and table 10.33 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.26 Example of Phase Counting Mode 2 Operation Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count Rev. 1.00 Jan. 29, 2008 Page 289 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 3. Phase counting mode 3 Figure 10.27 shows an example of phase counting mode 3 operation, and table 10.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.27 Example of Phase Counting Mode 3 Operation Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care Rev. 1.00 Jan. 29, 2008 Page 290 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 4. Phase counting mode 4 Figure 10.28 shows an example of phase counting mode 4 operation, and table 10.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.28 Example of Phase Counting Mode 4 Operation Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count Rev. 1.00 Jan. 29, 2008 Page 291 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode Application Example: Figure 10.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed. Rev. 1.00 Jan. 29, 2008 Page 292 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed period capture) TGRB_1 (speed period capture) TCNT_0 + + - TGRA_0 (speed control period) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 10.29 Phase Counting Mode Application Example 10.5 Interrupt Sources There are three kinds of TPU interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 10.36 lists the TPU interrupt sources. Rev. 1.00 Jan. 29, 2008 Page 293 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.36 TPU Interrupts Channel 0 Name TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 1 TGIA_1 TGIB_1 TCIV_1 TCIU_1 2 TGIA_2 TGIB_2 TCIV_2 TCIU_2 3 TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 4 TGIA_4 TGIB_4 TCIV_4 TCIU_4 5 TGIA_5 TGIB_5 TCIV_5 TCIU_5 Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TCNT_4 overflow TCNT_4 underflow TGRA_5 input capture/compare match TGRB_5 input capture/compare match TCNT_5 overflow TCNT_5 underflow DTC Interrupt Flag Activation TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TCFV_4 TCFU_4 TGFA_5 TGFB_5 TCFV_5 TCFU_5 Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Rev. 1.00 Jan. 29, 2008 Page 294 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5. 10.6 DTC Activation The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 8, Data Transfer Controller (DTC). A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. 10.7 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to begin A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is begun. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. Rev. 1.00 Jan. 29, 2008 Page 295 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.8 10.8.1 Operation Timing Input/Output Timing TCNT Count Timing: Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT count timing in external clock operation. Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.30 Count Timing in Internal Clock Operation External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.31 Count Timing in External Clock Operation Rev. 1.00 Jan. 29, 2008 Page 296 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.32 shows output compare output timing. TCNT input clock N N+1 TCNT TGR N Compare match signal TIOC pin Figure 10.32 Output Compare Output Timing Input Capture Signal Timing: Figure 10.33 shows input capture signal timing. Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 10.33 Input Capture Input Signal Timing Rev. 1.00 Jan. 29, 2008 Page 297 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.34 shows the timing when counter clearing on compare match is specified, and figure 10.35 shows the timing when counter clearing on input capture is specified. Compare match signal Counter clear signal TCNT N H'0000 TGR N Figure 10.34 Counter Clear Timing (Compare Match) Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 10.35 Counter Clear Timing (Input Capture) Rev. 1.00 Jan. 29, 2008 Page 298 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 10.36 and 10.37 show the timing in buffer operation. TCNT n n+1 Compare match signal TGRA, TGRB TGRC, TGRD n N N Figure 10.36 Buffer Operation Timing (Compare Match) Input capture signal TCNT N N+1 TGRA, TGRB TGRC, TGRD n N N+1 n N Figure 10.37 Buffer Operation Timing (Input Capture) Rev. 1.00 Jan. 29, 2008 Page 299 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.8.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10.38 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. TCNT input clock TCNT N N+1 TGR N Compare match signal TGF flag TGI interrupt Figure 10.38 TGI Interrupt Timing (Compare Match) TGF Flag Setting Timing in Case of Input Capture: Figure 10.39 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. Rev. 1.00 Jan. 29, 2008 Page 300 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10.39 TGI Interrupt Timing (Input Capture) TCFV Flag/TCFU Flag Setting Timing: Figure 10.40 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing. TCNT input clock TCNT (overflow) Overflow signal H'FFFF H'0000 TCFV flag TCIV interrupt Figure 10.40 TCIV Interrupt Setting Timing Rev. 1.00 Jan. 29, 2008 Page 301 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) TCNT input clock TCNT (underflow) Underflow signal H'0000 H'FFFF TCFU flag TCIU interrupt Figure 10.41 TCIU Interrupt Setting Timing Rev. 1.00 Jan. 29, 2008 Page 302 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.42 shows the timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status flag clearing by the DTC. TSR write cycle T1 T2 Address TSR address Write signal Status flag Interrupt request signal Figure 10.42 Timing for Status Flag Clearing by CPU DTC read cycle T1 T2 DTC write cycle T1 T2 Address Source address Destination address Status flag Interrupt request signal Figure 10.43 Timing for Status Flag Clearing by DTC Activation Rev. 1.00 Jan. 29, 2008 Page 303 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9 10.9.1 Usage Notes Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 21, Power-Down Modes. 10.9.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.44 shows the input clock conditions in phase counting mode. Phase Phase differdifferOverlap ence ence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 1.00 Jan. 29, 2008 Page 304 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where (N + 1) f: Counter frequency : Operating frequency N: TGR set value Conflict between TCNT Write and Clear Operations 10.9.4 If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.45 shows the timing in this case. TCNT write cycle T2 T1 Address TCNT address Write signal Counter clear signal TCNT N H'0000 Figure 10.45 Conflict between TCNT Write and Clear Operations Rev. 1.00 Jan. 29, 2008 Page 305 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9.5 Conflict between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.46 shows the timing in this case. TCNT write cycle T1 T2 Address TCNT address Write signal TCNT input clock N TCNT write data M TCNT Figure 10.46 Conflict between TCNT Write and Increment Operations Rev. 1.00 Jan. 29, 2008 Page 306 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9.6 Conflict between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the previous value is written. Figure 10.47 shows the timing in this case. TGR write cycle T1 T2 Address TGR address Write signal Compare match signal TCNT N N+1 Inhibited TGR N TGR write data M Figure 10.47 Conflict between TGR Write and Compare Match Rev. 1.00 Jan. 29, 2008 Page 307 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9.7 Conflict between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation will be that in the buffer prior to the write. Figure 10.48 shows the timing in this case. TGR write cycle T2 T1 Address Buffer register address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 10.48 Conflict between Buffer Register Write and Compare Match Rev. 1.00 Jan. 29, 2008 Page 308 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9.8 Conflict between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be that in the buffer after input capture transfer. Figure 10.49 shows the timing in this case. TGR read cycle T2 T1 Address TGR address Read signal Input capture signal TGR X M Internal data bus M Figure 10.49 Conflict between TGR Read and Input Capture Rev. 1.00 Jan. 29, 2008 Page 309 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9.9 Conflict between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.50 shows the timing in this case. TGR write cycle T2 T1 Address TGR address Write signal Input capture signal TCNT M TGR M Figure 10.50 Conflict between TGR Write and Input Capture Rev. 1.00 Jan. 29, 2008 Page 310 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9.10 Conflict between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.51 shows the timing in this case. Buffer register write cycle T2 T1 Address Buffer register address Write signal Input capture signal TCNT N TGR Buffer register M N M Figure 10.51 Conflict between Buffer Register Write and Input Capture Rev. 1.00 Jan. 29, 2008 Page 311 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9.11 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.52 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. TCNT input clock TCNT Counter clear signal TGF Disabled TCFV H'FFFF H'0000 Figure 10.52 Conflict between Overflow and Counter Clearing Rev. 1.00 Jan. 29, 2008 Page 312 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) 10.9.12 Conflict between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.53 shows the operation timing when there is conflict between TCNT write and overflow. TCNT write cycle T2 T1 Address TCNT address Write signal TCNT write data H'FFFF M TCNT TCFV flag Figure 10.53 Conflict between TCNT Write and Overflow 10.9.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 10.9.14 Interrupts in Module Stop Mode If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Rev. 1.00 Jan. 29, 2008 Page 313 of 666 REJ09B0427-0100 Section 10 16-Bit Timer Pulse Unit (TPU) Rev. 1.00 Jan. 29, 2008 Page 314 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) Section 11 Programmable Pulse Generator (PPG) The programmable pulse generator provides pulse outputs using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 2 and group 3) that can operate both simultaneously and independently. The block diagram of the PPG is shown in figure 11.1. 11.1 * * * * * * * Features 8-bit output data Two output groups Selectable output trigger signals Non-overlap mode Can operate in tandem with the data transfer controller (DTC) Settable inverted output Module stop mode can be set Rev. 1.00 Jan. 29, 2008 Page 315 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) Compare match signals NDERH Control logic PMR NDERL PCR PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Pulse output pins, group 3 PODRH Pulse output pins, group 2 Pulse output pins, group 1 PODRL Pulse output pins, group 0 NDRL NDRH Internal data bus [Legend] PMR: PCR: NDERH: NDERL: NDRH: NDRL: PODRH: PODRL: PPG output mode register PPG output control register Next data enable register H Next data enable register L Next data register H Next data register L Output data register H Output data register L Figure 11.1 Block Diagram of PPG Rev. 1.00 Jan. 29, 2008 Page 316 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.2 Input/Output Pins Table 11.1 summarizes the pin configuration of the PPG. Table 11.1 Pin Configuration Pin Name PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 I/O Output Output Output Output Output Output Output Output Group 2 pulse output Function Group 3 pulse output 11.3 Register Descriptions The PPG has the following registers. * * * * * * * * PPG output control register (PCR) PPG output mode register (PMR) Next data enable register H (NDERH) Next data enable register L (NDERL) Output data register H (PODRH) Output data register L (PODRL) Next data register H (NDRH) Next data register L (NDRL) Rev. 1.00 Jan. 29, 2008 Page 317 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis. The corresponding DDR also needs to be set to 1 in order to enable pulse output by the PPG. * NDERH Bit 7 6 5 4 3 2 1 0 Bit Name NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 8 to 15 When a bit is set to 1 for pulse output by NDRH, the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger. Values are not transferred from NDRH to PODRH for cleared bits. * NDERL Bit 7 6 5 4 3 2 1 0 Bit Name NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 0 to 7 When a bit is set to 1 for pulse output by NDRL, the value in the corresponding NDRL bit is transferred to the PODRL bit by the selected output trigger. Values are not transferred from NDRL to PODRL for cleared bits. Rev. 1.00 Jan. 29, 2008 Page 318 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. * PODRH Bit 7 6 5 4 3 2 1 0 Bit Name POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 8 to 15 For bits that have been set to pulse output by NDERH, the output trigger transfers NDRH values to this register during PPG operation. While NDERH is set to 1, the CPU cannot write to this register. While NDERH is cleared, the initial output value of the pulse can be set. * PODRL Bit 7 6 5 4 3 2 1 0 Bit Name POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 0 to 7 For bits that have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set. Rev. 1.00 Jan. 29, 2008 Page 319 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.3.3 Next Data Registers H, L (NDRH, NDRL) NDRH and NDRL are 8-bit readable/writable registers that store the data for the next pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. * NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit 7 6 5 4 3 2 1 0 Bit Name NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 8 to 15 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. If pulse output groups 2 and output pulse groups 3 have different output triggers, the upper 4 bits and the lower 4 bits are mapped to different addresses, as shown below. Bit 7 6 5 4 Bit Name NDR15 NDR14 NDR13 NDR12 Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W Description Next Data Register 12 to 15 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. Reserved These bits are always read as 1 and cannot be modified. 3 to 0 Rev. 1.00 Jan. 29, 2008 Page 320 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 7 to 4 3 2 1 0 NDR11 NDR10 NDR9 NDR8 0 0 0 0 R/W R/W R/W R/W Next Data Register 8 to11 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. * NDRL If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below. Bit 7 6 5 4 3 2 1 0 Bit Name NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 0 to 7 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. If pulse output groups 0 and output pulse groups 1 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses as shown below. Rev. 1.00 Jan. 29, 2008 Page 321 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) Bit 7 6 5 4 Bit Name NDR7 NDR6 NDR5 NDR4 Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W Description Next Data Register 4 to 7 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Reserved These bits are always read as 1 and cannot be modified. 3 to 0 Bit Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 7 to 4 3 2 1 0 NDR3 NDR2 NDR1 NDR0 0 0 0 0 R/W R/W R/W R/W Next Data Register 3 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Rev. 1.00 Jan. 29, 2008 Page 322 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.3.4 PPG Output Control Register (PCR) PCR is an 8-bit readable/writable register that selects output trigger signals on a group-by-group basis. For details on output trigger selection, see section 11.3.5, PPG Output Mode Register (PMR). Bit 7 6 Bit Name G3CMS1 G3CMS0 Initial Value 1 1 R/W R/W R/W Description Group 3 Compare Match Select 0 and 1 Select output trigger of pulse output group 3. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 5 4 G2CMS1 G2CMS0 1 1 R/W R/W Group 2 Compare Match Select 0 and 1 Select output trigger of pulse output group 2. 00: Compare match in TPC channel 0 01: Compare match in TPC channel 1 10: Compare match in TPC channel 2 11: Compare match in TPC channel 3 3 2 1 0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 1 1 1 1 R/W R/W R/W R/W Reserved Reserved Rev. 1.00 Jan. 29, 2008 Page 323 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.3.5 PPG Output Mode Register (PMR) The PMR is an 8-bit readable/writable register that selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values on compare match A or B of the TPU that becomes the output trigger. For details, see section 11.4.5, Non-Overlapping Pulse Output. Bit 7 Bit Name G3INV Initial Value 1 R/W R/W Description Group 3 Inversion Selects direct output or inverted output for pulse output group 3. 0: Inverted output 1: Direct output 6 G2INV 1 R/W Group 2 Inversion Selects direct output or inverted output for pulse output group 2. 0: Inverted output 1: Direct output 5, 4 3 G3NOV All 1 0 R/W R/W Reserved Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values at compare match A or B in the selected TPU channel) 2 G2NOV 0 R/W Group 2 Non-Overlap Selects normal or non-overlapping operation for pulse output group 2. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values at compare match A or B in the selected TPU channel) 1, 0 All 0 R/W Reserved Rev. 1.00 Jan. 29, 2008 Page 324 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.4 11.4.1 Operation Overview Figure 11.2 shows a block diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. The sequential output of up to 8 bits of data is possible by writing new output data to NDR before the next compare match. DDR NDER Q Output trigger signal C Q PODR D Pulse output pin Normal output/inverted output Q NDR D Internal data bus Figure 11.2 PPG Output Operation Rev. 1.00 Jan. 29, 2008 Page 325 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.2 Output Timing If pulse output is enabled, the contents of NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. TCNT N N+1 TGRA N Compare match A signal NDRH n PODRH m n PO8 to PO15 m n Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) Rev. 1.00 Jan. 29, 2008 Page 326 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.3 Sample Setup Procedure for Normal Pulse Output Figure 11.4 shows a sample procedure for setting up normal pulse output. Normal PPG output Select TGR functions Set TGRA value TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Port and PPG setup Select output trigger Set next pulse output data TPU setup Start counter Compare match? Yes Set next pulse output data [10] [3] [4] [5] [6] [7] [1] [2] [1] Set TIOR to make TGRA an output compare register (with output disabled) [2] Set the PPG output trigger period [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next output values in NDR. [8] [9] No Figure 11.4 Setup Procedure for Normal Pulse Output (Example) Rev. 1.00 Jan. 29, 2008 Page 327 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.4 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 11.5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value TGRA Compare match TCNT H'0000 NDRH 80 C0 40 60 20 30 10 18 08 88 80 C0 40 Time PODRH 00 80 C0 40 60 20 30 10 18 08 88 80 C0 PO15 PO14 PO13 PO12 PO11 Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output) 1. Set up TGRA of the TPU that is used as the output trigger to be an output compare register. Set a frequency in TGRA so the counter will be cleared on compare match A. Set the TGIEA bit of TIER to 1 to enable the compare match/input capture A (TGIA) interrupt. 2. Write H'F8 in P1DDR and NDERH, and set the G3CMS0, G3CMS1, G2CMS0, and G2CMS1 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. 3. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. 4. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU. Rev. 1.00 Jan. 29, 2008 Page 328 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.5 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: * NDR bits are always transferred on PODR bits on compare match A. * On compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 11.6 illustrates the non-overlapping pulse output operation. DDR NDER Q Compare match A Compare match B Pulse output pin C Q PODR D Q NDR D Internal data bus Normal output/inverted output Figure 11.6 Non-Overlapping Pulse Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval between compare match B and compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC. Note, however, that the next data must be written before the next compare match B occurs. Figure 11.7 shows the timing of this operation. Rev. 1.00 Jan. 29, 2008 Page 329 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) Compare match A Compare match B Write to NDR NDR Write to NDR PODR 0 output 0/1 output 0 output 0/1 output Write to NDR here Write to NDR Do not write here to NDR here Do not write to NDR here Figure 11.7 Non-Overlapping Operation and NDR Write Timing Rev. 1.00 Jan. 29, 2008 Page 330 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 11.8 shows a sample procedure for setting up non-overlapping pulse output. Non-overlapping PPG output Select TGR functions Set TGR values TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set non-overlapping groups Set next pulse output data TPU setup Start counter Compare match A? Yes Set next pulse output data [11] [11] At each TGIA interrupt, set the next output values in NDR. [3] [4] [5] [6] [7] [8] [1] [2] [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled) [2] Set the pulse output trigger period in TGRB and the non-overlap margin in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlap mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. PPG setup [9] [10] No Figure 11.8 Setup Procedure for Non-Overlapping Pulse Output (Example) Rev. 1.00 Jan. 29, 2008 Page 331 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.7 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 11.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time PODRH 00 95 05 65 41 59 50 56 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) Rev. 1.00 Jan. 29, 2008 Page 332 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 1. Set up the TPU channel to be used as the output trigger channel such that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared on compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH. 4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU. Rev. 1.00 Jan. 29, 2008 Page 333 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.8 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 11.9. TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time PODRL 00 95 05 65 41 59 50 56 14 95 05 65 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11.10 Inverted Pulse Output (Example) Rev. 1.00 Jan. 29, 2008 Page 334 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.4.9 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 11.11 shows the timing of this output. TIOC pin Input capture signal NDR N PODR M N PO M N Figure 11.11 Pulse Output Triggered by Input Capture (Example) Rev. 1.00 Jan. 29, 2008 Page 335 of 666 REJ09B0427-0100 Section 11 Programmable Pulse Generator (PPG) 11.5 11.5.1 Usage Notes Module Stop Mode Setting PPG operation can be disabled or enabled using the module stop control register. The initial setting is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 21, Power-Down Modes. 11.5.2 Operation of Pulse Output Pins Pins PO8 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur. Rev. 1.00 Jan. 29, 2008 Page 336 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) Section 12 Watchdog Timer (WDT) This LSI has a two-channel watchdog timer (WDT_0, WDT_1). WDT is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. The block diagrams of the WDT_0 and WDT_1 are shown in figures 12.1 and 12.2, respectively. 12.1 Features * Selectable from eight counter input clocks (WDT_0) or sixteen counter input clocks (WDT_1) * Switchable between watchdog timer mode and interval timer mode In watchdog timer mode: * If the counter overflows, it is possible to select whether this LSI is internally reset or not or whether an internal NMI interrupt is generated or not. In interval timer mode: * If the counter overflows, the WDT generates an interval timer interrupt (WOVI). Rev. 1.00 Jan. 29, 2008 Page 337 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) Overflow WOVI (interrupt request signal) Interrupt control Clock Clock select Internal reset signal* Reset control /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock sources Internal bus RSTCSR TCNT_0 TCSR_0 Bus interface Module bus WDT_0 [Legend] TCSR_0: Timer control/status register_0 TCNT_0: Timer counter_0 RSTCSR: Reset control/status register Note: * An internal reset signal can be generated by setting the register. Figure 12.1 Block Diagram of WDT_0 WOVI (interrupt request signal) Internal NMI interrupt request signal Internal reset signal* Interrupt control Overflow Reset control Clock Clock select /2 /64 /128 /512 /2048 /8192 /32768 /131072 Internal clock SUB/2 SUB/4 SUB/8 SUB/16 SUB/32 SUB/64 SUB/128 SUB/256 TCNT_1 TCSR_1 Bus interface Module bus WDT_1 [Legend] TCSR_1: Timer control/status register_1 TCNT_1: Timer counter_1 Note: * An internal reset signal can be generated by setting the register. Figure 12.2 Block Diagram of WDT_1 Rev. 1.00 Jan. 29, 2008 Page 338 of 666 REJ09B0427-0100 Internal bus Section 12 Watchdog Timer (WDT) 12.2 Register Descriptions The WDT has the following registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to by a different method to normal registers. For details, see section 12.5.1, Notes on Register Access. * * * * * Timer counter_0 (TCNT_0) Timer control/status register_0 (TCSR_0) Timer counter_1 (TCNT_1) Timer control/status register_1 (TCSR_1) Reset control/status register (RSTCSR) Timer Counter (TCNT) 12.2.1 TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 by a reset, when the TME bit in TCSR is cleared to 0. 12.2.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT and the timer mode. * TCSR_0 Bit 7 Bit Name OVF Initial Value 0 R/W Description R/(W)* Overflow Flag Indicates that TCNT has overflowed. Only a write of 0 is permitted, to clear the flag. [Setting conditions] * * When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. Cleared by reading TCSR when OVF = 1, then writing 0 to OVF [Clearing condition] * Rev. 1.00 Jan. 29, 2008 Page 339 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) Bit 6 Bit Name WT/IT Initial Value 0 R/W R/W Description Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4, 3 -- All 1 -- Reserved These bits are always read as 1 and cannot be modified. 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 These bits select the clock source to be input to TCNT. The overflow frequency for = 20 MHz is enclosed in parentheses. 000: Clock /2 (frequency: 25.6 s) 001: Clock /64 (frequency: 819.2 s) 010: Clock /128 (frequency: 1.6 ms) 011: Clock /512 (frequency: 6.6 ms) 100: Clock /2048 (frequency: 26.2 ms) 101: Clock /8192 (frequency: 104.9 ms) 110: Clock /32768 (frequency: 419.4 ms) 111: Clock /131072 (frequency: 1.68 s) Note: * Only 0 can be written, for flag clearing. Rev. 1.00 Jan. 29, 2008 Page 340 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) * TCSR_1 Bit 7 Bit Name OVF Initial Value 0 R/W Description R/(W)* Overflow Flag Indicates that TCNT has overflowed from H'FF to H'00. Only a write of 0 is permitted, to clear the flag. [Setting conditions] * * When TCNT overflows (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. Cleared by reading TCSR when OVF = 1, then writing 0 to OVF [Clearing condition] * 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode 1: Watchdog timer mode 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 PSS 0 R/W Prescaler Select Selects the clock source to be input to TCNT. 0: Counts the divided clock of -based prescaler (PSM) 1: Counts the divided clock of SUB-based prescaler (PSS) 3 RST/NMI 0 R/W Reset or NMI Selects whether an internal reset request or an NMI interrupt request when the TCNT overflows during the watchdog timer mode. 0: NMI interrupt request 1: Internal reset request Rev. 1.00 Jan. 29, 2008 Page 341 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) Bit 2 1 0 Bit Name CKS2 CKS1 CKS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Clock Select 2 to 0 Selects the clock source to be input to TCNT. The overflow cycle is the period from which TCNT starts incrementing at H'00 and until it overflows. When PSS = 0 (values in parentheses are for = 20 MHz): 000: /2 (cycle: 25.6 s) 001: /64 (cycle: 819.2 ms) 010: /128 (cycle: 1.6 ms) 011: /512 (cycle: 6.6 ms) 100: /2048 (cycle: 26.2 ms) 101: /8192 (cycle: 104.9 ms) 110: /32768 (cycle: 419.4 ms) 111: /131072 (cycle: 1.68 s) When PSS = 1 (values in parentheses are for SUB = 32.768 kHz): 000: SUB/2 (cycle: 15.6 ms) 001: SUB/4 (cycle: 31.3 ms) 010: SUB/8 (cycle: 62.5 ms) 011: SUB/16 (cycle: 125 ms) 100: SUB/32 (cycle: 250 ms) 101: SUB/64 (cycle: 500 ms) 110: SUB/128 (cycle: 1 s) 111: SUB/256 (cycle: 2 s) Note: * Only 0 can be written, for flag clearing. Rev. 1.00 Jan. 29, 2008 Page 342 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) 12.2.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by overflows. Bit 7 Bit Name WOVF Initial Value 0 R/W Description R/(W)* Watchdog Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] * Set when TCNT overflows (changed from H'FF to H'00) in watchdog timer mode Cleared by reading RSTCSR when WOVF = 1, and then writing 0 to WOVF [Clearing condition] * 6 RSTE 0 R/W Reset Enable Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog timer operation. 0: Reset signal is not generated even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: Reset signal is generated if TCNT overflows 5 RSTS 0 R/W Reset Select Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. 0: Power-on reset 1: Setting prohibited 4 to 0 -- All 1 -- Reserved These bits are always read as 1 and cannot be modified. Note: * Only 0 can be written, for flag clearing. Rev. 1.00 Jan. 29, 2008 Page 343 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) 12.3 12.3.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. When the WDT is used as a watchdog timer, and if TCNT overflows without being rewritten because of a system malfunction or other error, an internal reset can be generated. In the case of the WDT_0, when the TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. At this time, when the RSTE bit is set to 1, an internal reset signal for this LSI is output. The internal reset signal is output for 518 states. This is illustrated in figure 12.3 (a). If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. In the case of the WDT_1, the LSI is reset, or an NMI interrupt request is generated, for 516 system clock periods (516 ) (515 or 516 states when the clock source is SUB (PSS = 1)). This is illustrated in figure 12.3 (b). An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are both treated as having the same vector. So, avoid handling an NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin at the same time. Rev. 1.00 Jan. 29, 2008 Page 344 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 Write H'00 to TCNT WOVF = 1*1 Internal reset is generated Internal reset signal* 2 518 states [Legend] Timer mode select bit WT/IT: Timer enable bit TME: Notes: 1. After the WOVF bit becomes 1, it is cleared to 0 by an internal reset. 2. The internal reset signal is generated only if the RSTE bit is set to 1. Time WT/IT = 1 Write H'00 TME = 1 to TCNT Figure 12.3 (a) WDT_0 Operation in Watchdog Timer Mode TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 Write H'00 to TCNT WOVF = 1* Internal reset is generated WT/IT = 1 TME = 1 Write H'00 to TCNT Time Internal reset signal 515/516 states [Legend] WT/IT: Timer mode select bit TME: Timer enable bit Note: * After the WOVF bit becomes 1, it is cleared to 0 by an internal reset. Figure 12.3 (b) WDT_1 Operation in Watchdog Timer Mode Rev. 1.00 Jan. 29, 2008 Page 345 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) 12.3.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the time the OVF bit of the TCSR is set to 1. 12.4 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. If an NMI interrupt request has been selected in watchdog timer mode, an NMI interrupt request is generated when the TCNT overflows. Table 12.1 WDT Interrupt Sources Name WOVI NMI Interrupt Source TCNT overflow (interval timer mode) TCNT overflow (watchdog timer mode) Interrupt Flag OVF OVF Rev. 1.00 Jan. 29, 2008 Page 346 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) 12.5 12.5.1 Usage Notes Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT, TCSR, and RSTCSR These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address. Therefore, the relative condition shown in figure 12.4 needs to be satisfied in order to write to TCNT or TCSR. The transfer instruction writes the lower byte data to TCNT or TCSR according to the satisfied condition. To write to RSTCSR, execute a word transfer instruction for address H'FF76. A byte transfer instruction cannot write to RSTCSR. The method of writing 0 to the WOVF bit differs from that of writing to the RSTE and RSTS bits. To write 0 to the WOVF bit, satisfy the condition shown in figure 12.4. If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to the RSTE and RSTS bits, satisfy the condition shown in figure 12.4. If satisfied, the transfer instruction writes the values in bits 5 and 6 of the lower byte into the RSTE and RSTS bits, respectively, but has no effect on the WOVF bit. TCNT write Writing to RSTE and RSTS bits Address: H'FF74 H'FF76 15 H'5A 8 7 Write data 0 TCSR write Writing 0 to WOVF bit Address: H'FF74 H'FF76 15 H'A5 8 7 0 Write data or H'00 Figure 12.4 Writing to TCNT, TCSR, and RSTCSR (example for WDT0) Rev. 1.00 Jan. 29, 2008 Page 347 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) Reading TCNT, TCSR, and RSTCSR (WDT0) These registers are read in the same way as other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for RSTCSR. 12.5.2 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 12.5 shows this operation. TCNT write cycle T1 T2 Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.5 Contention between TCNT Write and Increment 12.5.3 Changing Value of CKS2 to CKS0 If bits CKS0 to CKS2 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS0 to CKS2. 12.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer while the WDT is operating, errors could occur in the incrementation. Software must be used to stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. Rev. 1.00 Jan. 29, 2008 Page 348 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) 12.5.5 Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, however TCNT and TCSR of the WDT are reset. TCNT, TCSR, or RSTCR cannot be written to for 132 states following an overflow. During this period, any attempt to read the WOVF flag is not acknowledged. Accordingly, wait 132 states after overflow to write 0 to the WOVF flag for clearing. 12.5.6 OVF Flag Clearing in Interval Timer Mode When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0 to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before writing 0 to the OVF bit to clear the flag. Rev. 1.00 Jan. 29, 2008 Page 349 of 666 REJ09B0427-0100 Section 12 Watchdog Timer (WDT) Rev. 1.00 Jan. 29, 2008 Page 350 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Section 13 Serial Communication Interface (SCI) This LSI has four independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports an IC card (smart card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Figure 13.1 shows a block diagram of the SCI. 13.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source (except for in Smart card interface mode). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Transmit-end, transmit-data-empty, receive-data-full, and receive error that can issue requests. The transmit-data-empty interrupt and receive data full interrupts can be used to activate the data transfer controller (DTC). * Module stop mode can be set Asynchronous mode * * * * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Rev. 1.00 Jan. 29, 2008 Page 351 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) * Break detection: Break can be detected by reading the RxD pin level directly in the case of a framing error Clocked Synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected Smart Card Interface * Automatic transmission of error signal (parity error) in receive mode * Error signal detection and automatic data retransmission in transmit mode * Direct convention and inverse convention both supported Bus interface Module data bus Internal data bus RDR TDR SCMR SSR SCR BRR Baud rate generator /4 /16 /64 Clock RxD RSR TSR SMR Transmission/ reception control TxD Parity generation Parity check SCK External clock TEI TXI RXI ERI [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register SCMR: Smart card mode register BRR: Bit rate register Figure 13.1 Block Diagram of SCI Rev. 1.00 Jan. 29, 2008 Page 352 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.2 Input/Output Pins Table 13.1 shows the serial pins for each SCI channel. Table 13.1 Pin Configuration Channel 0 Pin Name* SCK0 RxD0 TxD0 1 SCK1 RxD1 TxD1 2 SCK2 RxD2 TxD2 Note: * I/O I/O Input Output I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output SCI2 clock input/output SCI2 receive data input SCI2 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. Rev. 1.00 Jan. 29, 2008 Page 353 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.3 Register Descriptions The SCI has the following registers for each channel. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and smart card interface mode because their bit functions differ in part. * * * * * * * * * Receive shift register (RSR) Receive data register (RDR) Transmit data register (TDR) Transmit shift register (TSR) Serial mode register (SMR) Serial control register (SCR) Serial status register (SSR) Smart card mode register (SCMR) Bit rate register (BRR) Receive Shift Register (RSR) 13.3.1 RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 13.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU. Rev. 1.00 Jan. 29, 2008 Page 354 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. 13.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, and then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. 13.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bit functions of SMR differ between normal serial communication interface mode and smart card interface mode. * Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. Rev. 1.00 Jan. 29, 2008 Page 355 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Bit 5 Bit Name PE Initial Value 0 R/W R/W Description Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 0 and 1: These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 13.3.9, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 13.3.9, Bit Rate Register (BRR)). Rev. 1.00 Jan. 29, 2008 Page 356 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) * Smart Card Interface Mode (When SMIF in SCMR is 1) Bit 7 Bit Name GM Initial Value 0 R/W R/W Description GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of one bit), and clock output control mode addition is performed. For details, see section 13.7.8, Clock Output Control. 6 BLK 0 R/W When this bit is set to 1, the SCI operates in block transfer mode. For details on block transfer mode, see section 13.7.3, Block Transfer Mode. Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data in transmission, and the parity bit is checked in reception. In smart card interface mode, this bit must be set to 1. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. For details on setting this bit in smart card interface mode, see section 13.7.2, Data Format (Except for Block Transfer Mode). 3 2 BCP1 BCP0 0 0 R/W R/W Basic Clock Pulse 1 and 2 These bits specify the number of basic clock periods in a 1-bit transfer interval on the smart card interface. 00: 32 clock (S = 32) 01: 64 clock (S = 64) 10: 372 clock (S = 372) 11: 256 clock (S = 256) For details, see section 13.7.4, Receive Data Sampling Timing and Reception Margin in smart card Interface Mode. S stands for the value of S in BRR (see section 13.3.9, Bit Rate Register (BRR)). 5 PE 0 R/W Rev. 1.00 Jan. 29, 2008 Page 357 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Bit 1 0 Bit Name CKS1 CKS0 Initial Value 0 0 R/W R/W R/W Description Clock Select 0 and 1 These bits select the clock source for the baud rate generator. 00: clock (n = 0) 01: /4 clock (n = 1) 10: /16 clock (n = 2) 11: /64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 13.3.9, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 13.3.9, Bit Rate Register (BRR)). 13.3.6 Serial Control Register (SCR) SCR is a register that enables or disables SCI transfer operations and interrupt requests, and is also used to selection of the transfer clock source. For details on interrupt requests, see section 13.8, Interrupt Sources. Some bit functions of SCR differ between normal serial communication interface mode and smart card interface mode. * Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 TE RE 0 0 R/W R/W Transmit Enable When this bit s set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Rev. 1.00 Jan. 29, 2008 Page 358 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Bit 3 Bit Name MPIE Initial Value 0 R/W R/W Description Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 13.5, Multiprocessor Communication Function. 2 1 0 TEIE CKE1 CKE0 0 0 0 R/W R/W R/W Transmit End Interrupt Enable This bit is set to 1, TEI interrupt request is enabled. Clock Enable 0 and 1 Selects the clock source and SCK pin function. Asynchronous mode 00: Internal baud rate generator SCK pin functions as I/O port 01: Internal baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK pin. 1X: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK pin. Clocked synchronous mode 0X: Internal clock (SCK pin functions as clock output) 1X: External clock (SCK pin functions as clock input) [Legend] X: Don't care Rev. 1.00 Jan. 29, 2008 Page 359 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) * Smart Card Interface Mode (When SMIF in SCMR is 1) Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 3 TE RE MPIE 0 0 0 R/W R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in smart card interface mode. 2 1 0 TEIE CKE1 CKE0 0 0 0 R/W R/W R/W Transmit End Interrupt Enable Write 0 to this bit in smart card interface mode. Clock Enable 0 and 1 Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode. For details, see section 13.7.8, Clock Output Control. When the GM bit in SMR is 0: 00: Output disabled (SCK pin can be used as an I/O port pin) 01: Clock output 1X: Reserved When the GM bit in SMR is 1: 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output [Legend] X: Don't care Rev. 1.00 Jan. 29, 2008 Page 360 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ between normal serial communication interface mode and smart card interface mode. * Normal Serial Communication Interface Mode (When SMIF in SCMR is 0) Bit 7 Bit Name TDRE Initial Value 1 R/W R/W Description Transmit Data Register Empty Displays whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt request and writes data to TDR [Clearing conditions] * * 6 RDRF 0 R/W Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When the DTC is activated by an RXI interrupt and transferred data from RDR [Clearing conditions] * * The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. Rev. 1.00 Jan. 29, 2008 Page 361 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Bit 5 Bit Name ORER Initial Value 0 R/W R/W Description Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1 When 0 is written to ORER after reading ORER = 1 [Clearing condition] * 4 FER 0 R/W Framing Error [Setting condition] * * 3 PER 0 R/W When the stop bit is 0 When 0 is written to FER after reading FER = 1 [Clearing condition] In 2-stop-bit mode, only the first stop bit is checked. Parity Error [Setting condition] * * 2 TEND 1 R When a parity error is detected during reception When 0 is written to PER after reading PER = 1 [Clearing condition] Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and writes data to TDR [Clearing conditions] * * 1 MPB 0 R Multiprocessor Bit MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit data. Rev. 1.00 Jan. 29, 2008 Page 362 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) * Smart Card Interface Mode (When SMIF in SCMR is 1) Bit 7 Bit Name TDRE Initial Value 1 R/W R/W Description Transmit Data Register Empty Displays whether TDR contains transmit data. [Setting conditions] * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt request and writes data to TDR [Clearing conditions] * * 6 RDRF 0 R/W Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 When the DTC is activated by an RXI interrupt and transferred data from RDR [Clearing conditions] * * The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 5 ORER 0 R/W Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1 When 0 is written to ORER after reading ORER = 1 [Clearing condition] * 4 ERS 0 R/W Error Signal Status [Setting condition] * * When the low level of the error signal is sampled When 0 is written to ERS after reading ERS = 1 [Clearing conditions] Rev. 1.00 Jan. 29, 2008 Page 363 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Bit 3 Bit Name PER Initial Value 0 R/W R/W Description Parity Error [Setting condition] * * When a parity error is detected during reception When 0 is written to PER after reading PER = 1 [Clearing condition] 2 TEND 1 R Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR. [Setting conditions] * * When the TE bit in SCR is 0 and the ERS bit is also 0 When the ERS bit is 0 and the TDRE bit is 1 after the specified interval following transmission of 1byte data. The timing of bit setting differs according to the register setting as follows: When GM = 0 and BLK = 0, 2.5 etu after transmission starts When GM = 0 and BLK = 1, 1.5 etu after transmission starts When GM = 1 and BLK = 0, 1.0 etu after transmission starts When GM = 1 and BLK = 1, 1.0 etu after transmission starts [Clearing conditions] * * When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and writes data to TDR 1 0 MPB MPBT 0 0 R R/W Multiprocessor Bit This bit is not used in smart card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in smart card interface mode. Rev. 1.00 Jan. 29, 2008 Page 364 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.3.8 Smart Card Mode Register (SCMR) SCMR is a register that selects smart card interface mode and its format. Bit Bit Name Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1. 3 SDIR Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data format is 8 bits. For 7-bit data, LSB-first is fixed. 2 SINV 0 R/W Smart Card Data Invert Specifies inversion of the data logic level. The SINV bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR 1 0 SMIF 1 0 R/W Reserved This bit is always read as 1. Smart Card Interface Mode Select This bit is set to 1 to make the SCI operate in smart card interface mode. 0: Normal asynchronous mode or clocked synchronous mode 1: Smart card interface mode 7 to 4 Rev. 1.00 Jan. 29, 2008 Page 365 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 13.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and it can be read or written to by the CPU at all times. Table 13.2 The Relationships between The N Setting in BRR and Bit Rate B Mode Asynchronous Mode Clocked Synchronous Mode Smart Card Interface Mode [Legend] B: N: : n and S: BRR Setting N N= N= x 106 64 x 2 2n-1 Error -1 -1 x 106 B x S x 2 2n+1 x (N + 1) Error (%) = { x 106 B x 64 x 2 2n-1 x (N + 1) - 1 } x 100 xB x 106 8 x 2 2n-1 x B x 106 Sx2 2n+1 N= xB - 1 Error (%) = { - 1 } x 100 Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Determined by the SMR settings shown in the following tables. SMR Setting SMR Setting n 0 1 2 3 BCP1 0 0 1 1 BCP0 0 1 0 1 S 32 64 372 256 CKS1 0 0 1 1 CKS0 0 1 0 1 Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 13.6 shows sample N settings in BRR in clocked synchronous mode. Table 13.8 shows sample N settings in BRR in smart card interface mode. In smart card interface mode, S (the number of basic clock periods in a 1-bit transfer interval) can be selected. For details, see section 13.7.4, Receive Data Sampling Timing and Reception Margin in smart card Interface Mode. Tables 13.5 and 13.7 show the maximum bit rates with external clock input. Rev. 1.00 Jan. 29, 2008 Page 366 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency (MHz) Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 4 n 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 4.9152 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 Operating Frequency (MHz) 6 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0.00 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 9 5 4 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 7.3728 N 130 95 191 95 191 95 47 23 11 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 2 2 1 1 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 Rev. 1.00 Jan. 29, 2008 Page 367 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency (MHz) 9.8304 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 Operating Frequency (MHz) 14 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 Error (%) -0.17 0.13 0.13 0.13 0.13 0.13 0.13 -0.93 -0.93 0.00 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 17.2032 N 75 223 111 223 111 223 111 55 27 13 13 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 Rev. 1.00 Jan. 29, 2008 Page 368 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency (MHz) 18 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) (MHz) 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 230400 250000 307200 312500 n 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 (MHz) 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 Maximum Bit Rate (bit/s) 375000 384000 437500 460800 500000 537600 562500 614400 625000 n 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 Rev. 1.00 Jan. 29, 2008 Page 369 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) (MHz) 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 External Input Clock (MHz) 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 Maximum Bit Rate (bit/s) 62500 76800 78125 93750 96000 115200 125000 153600 156250 (MHz) 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bit/s) 187500 192000 218750 230400 250000 268800 281250 307200 312500 Rev. 1.00 Jan. 29, 2008 Page 370 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M [Legend] Blank: Setting prohibited. : Can be set, but there will be a degree of error. *: Continuous transfer is not possible. 4 n 2 2 1 1 0 0 0 0 0 0 0 0 N 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 124 249 124 199 99 199 79 39 19 7 3 1 0 0* 1 1 0 0 0 0 0 0 249 124 249 99 49 24 9 4 3 3 2 2 1 1 0 0 0 0 0 0 249 124 249 99 199 99 159 79 39 15 7 3 2 1 1 0 0 0 0 0 0 0 0 124 249 124 199 99 49 19 9 4 1 0* n 8 N n 10 N n 16 N n 20 N Table 13.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) (MHz) 4 6 8 10 12 External Input Clock (MHz) 0.6667 1.0000 1.3333 1.6667 2.0000 Maximum Bit Rate (bit/s) 666666.7 1.000000.0 1333333.3 1666666.7 2000000.0 (MHz) 14 16 18 20 External Input Clock (MHz) 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 2333333.3 2666666.7 3000000.0 3333333.3 Rev. 1.00 Jan. 29, 2008 Page 371 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Table 13.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (When n = 0 and S = 372) Operating Frequency (MHz) 7.1424 Bit Rate (bit/s) 9600 n 0 N 0 Error (%) 0.00 n 0 10.00 N 1 Error (%) 30 n 0 10.7136 N 1 Error (%) 25 n 0 13.00 N 1 Error (%) 8.99 Operating Frequency (MHz) 14.2848 Bit Rate (bit/s) 9600 n 0 N 1 Error (%) 0.00 n 0 16.00 N 1 Error (%) 12.01 n 0 18.00 N 2 Error (%) 15.99 n 0 20.00 N 2 Error (%) 6.60 Table 13.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) (MHz) 7.1424 10.00 10.7136 13.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 n 0 0 0 0 N 0 0 0 0 (MHz) 14.2848 16.00 18.00 20.00 Maximum Bit Rate (bit/s) 19200 21505 24194 26882 n 0 0 0 0 N 0 0 0 0 Rev. 1.00 Jan. 29, 2008 Page 372 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.4 Operation in Asynchronous Mode Figure 13.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line. When the transmission line goes to the space state (low level), the SCI recognizes a start bit and starts serial communication. In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. Idle state (mark state) 1 0/1 Parity bit 1 bit, or none 1 1 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 13.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 13.4.1 Data Transfer Format Table 13.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 13.5, Multiprocessor Communication Function. Rev. 1.00 Jan. 29, 2008 Page 373 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Table 13.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S S S S S S S S S S S S 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP STOP STOP P STOP P STOP STOP STOP STOP P STOP P STOP STOP MPB STOP MPB STOP STOP MPB STOP MPB STOP STOP [Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev. 1.00 Jan. 29, 2008 Page 374 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 13.3. Thus, the reception margin in asynchronous mode is given by formula (1) below. M = { (0.5 - 1 D - 0.5 )- 2N N - (L - 0.5) F} x 100 [%] ... Formula (1) Where N: Ratio of bit rate to clock (N = 16) D: Clock duty cycle (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock rate deviation Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty cycle) = 0.5 in formula (1), the reception margin can be given by the formula. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed for in system design. 16 clocks 8 clocks 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0 Start bit D0 D1 Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode Rev. 1.00 Jan. 29, 2008 Page 375 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13.4. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 13.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) Rev. 1.00 Jan. 29, 2008 Page 376 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Start initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE and RE bits are cleared to 0.) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Figure 13.5 Sample SCI Initialization Flowchart Rev. 1.00 Jan. 29, 2008 Page 377 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.4.5 Data Transmission (Asynchronous Mode) Figure 13.6 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Continuous transmission is possible because the TXI interrupt routine writes next transmit data to TDR before transmission of the current transmit data has been completed. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 13.7 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt service routine TEI interrupt request generated 1 frame Figure 13.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 1.00 Jan. 29, 2008 Page 378 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Figure 13.7 Sample Serial Transmission Flowchart Rev. 1.00 Jan. 29, 2008 Page 379 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.4.6 Serial Data Reception (Asynchronous Mode) Figure 13.8 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line. If a start bit is detected, the SCI performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has been completed. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ERI interrupt request generated by framing error 1 frame Figure 13.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 1.00 Jan. 29, 2008 Page 380 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Table 13.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.9 shows a sample flow chart for serial data reception. Table 13.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains the state it had before data reception. Rev. 1.00 Jan. 29, 2008 Page 381 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PERFERORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No Error processing resumed if any of these flags are set to 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin. Read ORER, PER, and FER flags in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when DTC is activated by an RXI interrupt and the RDR value is read. No All data received? Yes Clear RE bit in SCR to 0 Figure 13.9 Sample Serial Reception Data Flowchart (1) Rev. 1.00 Jan. 29, 2008 Page 382 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 13.9 Sample Serial Reception Data Flowchart (2) Rev. 1.00 Jan. 29, 2008 Page 383 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 13.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER to 1, are inhibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 1.00 Jan. 29, 2008 Page 384 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 (MPB = 1) Receiving station C (ID = 03) H'AA (MPB = 0) Receiving station D (ID = 04) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 13.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev. 1.00 Jan. 29, 2008 Page 385 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.5.1 Multiprocessor Serial Data Transmission Figure 13.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Rev. 1.00 Jan. 29, 2008 Page 386 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to 1, clear DR to 0, then clear the TE bit in SCR to 0. No TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes No Break output? Yes [4] Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart Rev. 1.00 Jan. 29, 2008 Page 387 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.5.2 Multiprocessor Serial Data Reception Figure 13.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 13.12 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data1) D1 D7 Stop MPB bit 0 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station's ID 1 Start bit 0 D0 D1 Data (ID2) D7 Stop MPB bit 1 1 Start bit 0 D0 Data (Data2) D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine Data2 MPIE bit set to 1 again (b) Data matches station's ID Figure 13.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 1.00 Jan. 29, 2008 Page 388 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin [4] value. Read MPIE bit in SCR Read ORER and FER flags in SSR [2] Yes FERORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR Yes FERORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 1.00 Jan. 29, 2008 Page 389 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 1.00 Jan. 29, 2008 Page 390 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.6 Operation in Clocked Synchronous Mode Figure 13.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronous with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication through the use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so data can be read or written during transmission or reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note:* High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 13.14 Data Format in Synchronous Communication (For LSB-First) 13.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of CKE0 and CKE1 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Rev. 1.00 Jan. 29, 2008 Page 391 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, the TE and RE bits in SCR should be cleared to 0, then the SCI should be initialized as described in a sample flowchart in figure 13.15. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Start initialization [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. [1] Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Note:* In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 13.15 Sample SCI Initialization Flowchart Rev. 1.00 Jan. 29, 2008 Page 392 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 13.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. Continuous transmission is possible because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has been completed. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified, and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 13.17 shows a sample flow chart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure that the receive error flags are cleared to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Rev. 1.00 Jan. 29, 2008 Page 393 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Transfer direction Synchronization clock Serial data TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 13.16 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev. 1.00 Jan. 29, 2008 Page 394 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Initialization Start transmission [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND = 1 Yes Clear TE bit in SCR to 0 Figure 13.17 Sample Serial Transmission Flowchart Rev. 1.00 Jan. 29, 2008 Page 395 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 13.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization synchronous with a synchronous clock input or output, starts receiving data, and stores the received data in RSR. 2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag in SSR is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the RDRF flag remains to be set to 1. 3. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished. Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 13.18 Example of SCI Operation in Reception Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.19 shows a sample flow chart for serial data reception. Rev. 1.00 Jan. 29, 2008 Page 396 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. The RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. Read ORER flag in SSR [2] Yes ORER = 1 No [3] Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 13.19 Sample Serial Reception Flowchart Rev. 1.00 Jan. 29, 2008 Page 397 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 13.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after initializing the SCI. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction. Rev. 1.00 Jan. 29, 2008 Page 398 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Initialization Start transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] [3] Read ORER flag in SSR Yes [3] Error processing ORER = 1 No [4] Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Figure 13.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev. 1.00 Jan. 29, 2008 Page 399 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.7 Operation in Smart Card Interface The SCI supports an IC card (smart card) interface that conforms to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the smart card interface mode is carried out by means of a register setting. 13.7.1 Pin Connection Example Figure 13.21 shows an example of connection with the smart card. In communication with an IC card, as both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected to the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. When the clock generated on the smart card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal. VCC TxD RxD SCK Rx (port) This LSI Connected equipment Data line Clock line Reset line I/O CLK RST IC card Figure 13.21 Schematic Diagram of Smart Card Interface Pin Connections Rev. 1.00 Jan. 29, 2008 Page 400 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.7.2 Data Format (Except for Block Transfer Mode) Figure 13.22 shows the transfer data format in smart card interface mode. * One frame consists of 8-bit data plus a parity bit in asynchronous mode. * In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. * If an error signal is sampled during transmission, the same data is retransmitted automatically after a delay of 2 etu or longer. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Receiving station output Start bit Data bits Parity bit Error signal [Legend] DS: D0 to D7: Dp: DE: Figure 13.22 Normal Smart Card Interface Data Format Data transfer with other types of IC cards (direct convention and inverse convention) are performed as described in the following. (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State Figure 13.23 Direct Convention (SDIR = SINV = O/E = 0) Rev. 1.00 Jan. 29, 2008 Page 401 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) With the direction convention type IC and the above sample start character, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to smart card regulations, clear the O/E bit in SMR to 0 to select even parity mode. (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State Figure 13.24 Inverse Convention (SDIR = SINV = O/E = 1) With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data for the above is H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to smart card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z. In this LSI, the SINV bit inverts only data bits D0 to D7. Therefore, set the O/E bit in SMR to 1 to invert the parity bit for both transmission and reception. 13.7.3 Block Transfer Mode Operation in block transfer mode is the same as that in SCI asynchronous mode, except for the following points. * In reception, though the parity check is performed, no error signal is output even if an error is detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the parity bit of the next frame. * In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the start of the next frame. * In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu after transmission start. * As with the normal smart card interface, the ERS flag indicates the error signal status, but since error signal transfer is not performed, this flag is always cleared to 0. Rev. 1.00 Jan. 29, 2008 Page 402 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode In smart card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed at 16 times in normal asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. As shown in figure 13.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the following formula. M = | (0.5 - 1 | D - 0.5 | ) - (L - 0.5) F - (1 + F) | x 100% 2N N Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, and 256) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin formula is as follows. M = (0.5 - 1/2 x 372) x 100% = 49.866% Rev. 1.00 Jan. 29, 2008 Page 403 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 372 clocks 186 clocks 0 Internal basic clock 185 371 0 185 371 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 13.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Transfer Rate) 13.7.5 Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. 2. 3. 4. Clear the TE and RE bits in SCR to 0. Clear the error flags ERS, PER, and ORER in SSR to 0. Set the GM, BLK, O/E, BCP0, BCP1, CKS0, and CKS1 bits in SMR. Set the PE bit to 1. Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. 5. Set the value corresponding to the bit rate in BRR. 6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. 7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. To switch from receive mode to transmit mode, after checking that the SCI has finished reception, initialize the SCI, and set RE to 0 and TE to 1. Whether SCI has finished reception or not can be checked with the RDRF, PER, or ORER flags. To switch from transmit mode to receive mode, Rev. 1.00 Jan. 29, 2008 Page 404 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) after checking that the SCI has finished transmission, initialize the SCI, and set TE to 0 and RE to 1. Whether SCI has finished transmission or not can be checked with the TEND flag. 13.7.6 Data Transmission (Except for Block Transfer Mode) As data transmission in smart card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 13.26 illustrates the retransfer operation when the SCI is in transmit mode. 1. If an error signal is sent back from the receiving end after transmission of one frame is complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. 2. The TEND bit in SSR is not set for a frame in which an error signal indicating an abnormality is received. Data is retransferred from TDR to TSR, and retransmitted automatically. 3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. Transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. Writing transmit data to TDR transfers the next transmit data. Figure 13.28 shows a flowchart for transmission. The sequence of transmit operations can be performed automatically by specifying the DTC to be activated with a TXI interrupt source. In a transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in SSR is set, and a TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data is transferred by the DTC. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC is not activated. Therefore, the SCI and DTC will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DTC, it is essential to set and enable the DTC before carrying out SCI setting. For details of the DTC setting procedures, see section 8, Data Transfer Controller (DTC). Rev. 1.00 Jan. 29, 2008 Page 405 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] FER/ERS [6] Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Transfer frame n+1 Ds D0 D1 D2 D3 D4 Transfer to TSR from TDR Transfer to TSR from TDR [9] [8] Figure 13.26 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 13.27. I/O data TXI (TEND interrupt) When GM = 0 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5etu 11.0etu When GM = 1 [Legend] Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 13.27 TEND Flag Generation Timing in Transmission Operation Rev. 1.00 Jan. 29, 2008 Page 406 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Start Initialization Start transmission ERS = 0? Yes No Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 13.28 Example of Transmission Processing Flow Rev. 1.00 Jan. 29, 2008 Page 407 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.7.7 Serial Data Reception (Except for Block Transfer Mode) Data reception in smart card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 13.29 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. 2. The RDRF bit in SSR is not set for a frame in which an error has occurred. 3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. Figure 13.30 shows a flowchart for reception. A sequence of receive operations can be performed automatically by specifying the DTC to be activated using an RXI interrupt source. In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be activated by the RXI request, and the receive data will be transferred. The RDRF flag is cleared to 0 automatically when data is transferred by the DTC. If an error occurs in receive mode and the ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. Hence, so the error flag must be cleared to 0. In the event of an error, the DTC is not activated and receive data is skipped. Therefore, receive data is transferred for only the specified number of bytes in the event of an error. Even when a parity error occurs in receive mode and the PER flag is set to 1, the data that has been received is transferred to RDR and can be read from there. Note: For details on receive operations in block transfer mode, see section 13.4, Operation in Asynchronous Mode. Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp [4] [3] Figure 13.29 Retransfer Operation in SCI Receive Mode Rev. 1.00 Jan. 29, 2008 Page 408 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Start Initialization Start reception ORER = 0 and PER = 0 Yes No Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 13.30 Example of Reception Processing Flow Rev. 1.00 Jan. 29, 2008 Page 409 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.7.8 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 13.31 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. CKE0 SCK Specified pulse width Specified pulse width Figure 13.31 Timing for Fixing Clock Output Level When turning on the power or switching between smart card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty cycle. Powering On: To secure clock duty cycle from power-on, the following switching procedure should be followed. 1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. 2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR. 3. Set SMR and SCMR, and switch to smart card mode operation. 4. Set the CKE0 bit in SCR to 1 to start clock output. When changing from smart card interface mode to software standby mode: 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. 2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to halt the clock. 4. Wait for one serial clock period. Rev. 1.00 Jan. 29, 2008 Page 410 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) During this interval, clock output is fixed at the specified level, with the duty cycle preserved. 5. Make the transition to the software standby state. When returning to smart card interface mode from software standby mode: 1. Exit the software standby state. 2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the normal duty cycle. Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] Figure 13.32 Clock Halt and Restart Procedure Rev. 1.00 Jan. 29, 2008 Page 411 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.8 13.8.1 Interrupt Sources Interrupts in Normal Serial Communication Interface Mode Table 13.12 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data is transferred by the DTC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt request can activate the DTC to transfer data. The RDRF flag is cleared to 0 automatically when data is transferred by the DTC. A TEI interrupt is requested when the TEND flag is set to 1 and the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Rev. 1.00 Jan. 29, 2008 Page 412 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Table 13.12 SCI Interrupt Sources Channel 0 Name ERI_0 RXI_0 TXI_0 TEI_0 1 ERI_1 RXI_1 TXI_1 TEI_1 2 ERI_2 RXI_2 TXI_2 TEI_2 Interrupt Source Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Rev. 1.00 Jan. 29, 2008 Page 413 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.8.2 Interrupts in Smart Card Interface Mode Table 13.13 shows the interrupt sources in smart card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Table 13.13 SCI Interrupt Sources Channel 0 Name ERI_0 RXI_0 TXI_0 1 ERI_0 RXI_0 TXI_0 2 ERI_2 RXI_2 TXI_2 Interrupt Source Receive Error, error signal detection Receive Data Full Transmit Data Empty Receive Error, error signal detection Receive Data Full Transmit Data Empty Receive Error, error signal detection Receive Data Full Transmit Data Empty Interrupt Flag ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND ORER, PER, ERS RDRF TEND DTC Activation Not possible Possible Possible Not possible Possible Possible Not possible Possible Possible In smart card interface mode, as in normal serial communication interface mode, transfer can be carried out using the DTC. In transmit operations, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR is set, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transmit data will be transferred. The TDRE and TEND flags are automatically cleared to 0 when data is transferred by the DTC. In the event of an error, the SCI retransmits the same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC is not activated. Therefore, the SCI and DTC will automatically transmit the specified number of bytes in the event of an error, including retransmission. However, the ERS flag is not cleared automatically when an error occurs. Hence, the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When transferring using the DTC, it is essential to set and enable the DTC before carrying out SCI setting. For details of the DTC setting procedures, see section 8, Data Transfer Controller (DTC). In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be activated by the RXI request, and the receive data will be transferred. The RDRF flag is cleared to Rev. 1.00 Jan. 29, 2008 Page 414 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 0 automatically when data is transferred by the DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC is not activated, instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. Rev. 1.00 Jan. 29, 2008 Page 415 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.9 13.9.1 Usage Notes Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 21, Power-Down Modes. 13.9.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 13.9.3 Mark State and Break Detection When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line at mark state until TE is set to 1, set both DDR and DR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 13.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Rev. 1.00 Jan. 29, 2008 Page 416 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.9.5 Restrictions on Using DTC When the external clock source is used as a synchronization clock, update TDR by the DTC and wait for at least five clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 13.33). When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC activation source. SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When external clock is supplied, t must be more than four clock cycles. Figure 13.33 Sample Transmission using DTC in Clocked Synchronous Mode 13.9.6 SCI Operations during Mode Transitions Transmission: Before making the transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode is cancelled and then the TE is set to 1 again. If the transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. Figure 13.34 shows a sample flowchart for mode transition during transmission. Figures 13.35 and 13.36 show the pin states during transmission. Rev. 1.00 Jan. 29, 2008 Page 417 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Before making the transition from the transmission mode using DTC transfer to module stop, software standby, watch, sub-active, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). Setting TE and TIE to 1 after mode cancellation generates a TXI interrupt request to start transmission using the DTC. Transmission All data transmitted? Yes Read TEND flag in SSR No [1] TEND = 1 Yes TE = 0 [2] No [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing TDRE to 0 after mode cancellation; however, if the DTC has been initiated, the data remaining in DTC RAM will be transmitted when TE and TIE are set to 1. [2] Also clear TIE and TEIE to 0 when they are 1. Make transition to software standby mode etc. Cancel software standby mode etc. [3] [3] Module stop, watch, sub-active, and sub-sleep modes are included. Change operating mode? Yes Initialization No TE = 1 Start transmission Figure 13.34 Sample Flowchart for Mode Transition during Transmission Rev. 1.00 Jan. 29, 2008 Page 418 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Transmission start Transition to Software standby Transmission end software standby mode cancelled mode TE bit SCK output pin TxD output pin Port input/output Port input/output High output Start SCI TxD output Stop Port input/output Port High output SCI TxD output Port Figure 13.35 Pin States during Transmission in Asynchronous Mode (Internal Clock) Transition to Software standby software standby mode cancelled mode Transmission start Transmission end TE bit SCK output pin TxD output pin Port input/output Port input/output Marking output SCI TxD output Last TxD bit retained Port input/output Port High output* SCI TxD output Port Note: Initialized in software standby mode Figure 13.36 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock) Reception: Before making the transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 13.37 shows a sample flowchart for mode transition during reception. Rev. 1.00 Jan. 29, 2008 Page 419 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) Reception Read RDRF flag in SSR RDRF = 1 Yes Read receive data in RDR No [1] [1] Data being received will be invalid. RE = 0 [2] [2] Module stop, watch, sub-active, and subsleep modes are included. Make transition to software standby mode etc. Cancel software standby mode etc. Change operating mode? Yes Initialization No RE = 1 Start reception Figure 13.37 Sample Flowchart for Mode Transition during Reception Rev. 1.00 Jan. 29, 2008 Page 420 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) 13.9.7 Notes when Switching from SCK Pin to Port Pin * Problem in Operation: When DDR and DR are set to 1, SCI clock output is used in clocked synchronous mode, and the SCK pin is changed to the port pin while transmission is ended, port output is enabled after low-level output occurs for one half-cycle. When switching the SCK pin to the port pin by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, low-level output occurs for one halfcycle. 1. End of serial data transmission 2. TE bit = 0 3. C/A bit = 0 ... switchover to port output 4. Occurrence of low-level output (see figure 13.38) Half-cycle low-level output SCK/port 1. End of transmission Data TE C/A CKE1 CKE0 Bit 6 Bit 7 2. TE = 0 4. Low-level output 3. C/A = 0 Figure 13.38 Operation when Switching from SCK Pin to Port Pin Rev. 1.00 Jan. 29, 2008 Page 421 of 666 REJ09B0427-0100 Section 13 Serial Communication Interface (SCI) * Usage Note: To prevent low-level output occurred when switching the SCK pin to port pin, follow the procedure described below. As this sample procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. 1. End of serial data transmission 2. TE bit = 0 3. CKE1 bit = 1 4. C/A bit = 0 ... switchover to port output 5. CKE1 bit = 0 High-level output SCK/port 1. End of transmission Data TE C/A 3. CKE1 = 1 CKE1 CKE0 5. CKE1 = 0 Bit 6 Bit 7 2. TE = 0 4. C/A = 0 Figure 13.39 Operation when Switching from SCK Pin to Port Pin (Example of Preventing Low-Level Output) Rev. 1.00 Jan. 29, 2008 Page 422 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Section 14 I2C Bus Interface This LSI has a two-channel I2C bus interface. The conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Each I2C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer data, saving board and connector space. 14.1 Features * Selection of addressing format or non-addressing format I2C bus format: addressing format with acknowledge bit, for master/slave operation Serial format: non-addressing format without acknowledge bit, for master operation only * Conforms to Philips I2C bus interface (I2C bus format) * Two ways of setting slave address (I2C bus format) * Start and stop conditions generated automatically in master mode (I2C bus format) * Selection of acknowledge output levels when receiving (I2C bus format) * Automatic loading of acknowledge bit when transmitting (I2C bus format) * Wait function in master mode (I2C bus format) A wait can be inserted by driving the SCL pin low after data transfer, excluding acknowledgement. The wait can be cleared by clearing the interrupt flag. * Wait function in slave mode (I2C bus format) A wait request can be generated by driving the SCL pin low after data transfer, excluding acknowledgement. The wait request is cleared when the next transfer becomes possible. * Three interrupt sources Data transfer end (including transmission mode transition with I2C bus format and address reception after loss of master arbitration) Address match: when any slave address matches or the general call address is received in slave receive mode (I2C bus format) Stop condition detection * Selection of 16 internal clocks (in master mode) * Direct bus drive (with SCL and SDA pins) Two pins--P35/SCL0 and P34/SDA0--(normally NMOS push-pull outputs) function as NMOS open-drain outputs when the bus drive function is selected. Rev. 1.00 Jan. 29, 2008 Page 423 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Two pins--P33/SCL1 and P32/SDA1--(normally CMOS pins) function as NMOS-only outputs when the bus drive function is selected. Figure 14.1 shows a block diagram of the I2C bus interface. Figure 14.2 shows an example of I/O pin connections to external circuits. Channel 0 I/O pins are NMOS open drains, and it is possible to apply voltages in excess of the power supply (VCC) voltage for this LSI. Set the upper limit of voltage applied to the power supply (VCC) power supply range + 0.3 V, i.e. 5.8 V. Channel 1 I/O pins are driven solely by NMOS, so in terms of appearance they carry out the same operations as an NMOS open drain. However, the voltage which can be applied to the I/O pins depends on the voltage of the power supply (VCC) of this LSI. Rev. 1.00 Jan. 29, 2008 Page 424 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 SCL PS ICCR Clock control Noise canceler Bus state decision circuit Arbitration decision circuit ICMR ICSR ICDRT SDA Output data control circuit ICDRS ICDRR Noise canceler Address comparator SAR, SARX Legend: ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register SAR: Slave address register SARX: Second slave address register X PS: Prescaler Interrupt generator Interrupt request Figure 14.1 Block Diagram of I2C Bus Interface Rev. 1.00 Jan. 29, 2008 Page 425 of 666 REJ09B0427-0100 Internal data bus Section 14 I C Bus Interface 2 VCC VCC SCL SCLin SCLout SDA SCL SDA SDAin SDAout SCL SDA (Master) Chip SCLin SCLout SCLin SCLout SDAin SDAout (Slave 1) SDAin SDAout (Slave 2) Figure 14.2 I2C Bus Interface Connections (Example: The Chip as Master) 14.2 Input/Output Pins Table 14.1 summarizes the input/output pins used by the I2C bus interface. Table 14.1 I2C Bus Interface Pins Channel 0 1 Name Serial clock Serial data Serial clock Serial data Abbreviation SCL0 SDA0 SCL1 SDA1 I/O I/O I/O I/O I/O Function IIC_0 serial clock input/output IIC_0 serial data input/output IIC_1 serial clock input/output IIC_1 serial data input/output Note: In the text, the channel subscript is omitted, and only SCL and SDA are used. Rev. 1.00 Jan. 29, 2008 Page 426 of 666 REJ09B0427-0100 SCL SDA Section 14 I C Bus Interface 2 14.3 Register Configuration The I2C bus interface consists of the following registers per channel. ICDR, SARX, and ICMR are assigned to the same address. Register selection is performed by means of the IICE bit in the serial control register X (SCRX). * * * * * * * * I2C bus control register (ICCR) I2C bus status register (ICSR) I2C bus data register (ICDR) I2C bus mode register (ICMR) Slave address register (SAR) Second slave address register (SARX) Serial control register X (SCRX) DDC switch register (DDCSWR) 14.3.1 I2C Bus Data Register (ICDR) ICDR is an 8-bit readable/writable register that functions as a transmit data register when transmitting and a receive data register when receiving. ICDR is divided internally into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the three registers are performed automatically in coordination with changes in the bus state, and affect the status of internal flags such as TDRE and RDRF. If IIC is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRT to ICDRS. If IIC is in receive mode and no previous data remains in ICDRR (the RDRF flag is 0) following transmission/reception of one frame of data using ICDRS, data is transferred automatically from ICDRS to ICDRR. If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and receive data are stored differently. Transmit data should be written justified toward the MSB side when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1. ICDR is assigned to the same address as SARX, and can be written and read only when the ICE bit is set to 1 in ICCR. Rev. 1.00 Jan. 29, 2008 Page 427 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 The value of ICDR is undefined after a reset. The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the TDRE and RDRF flags affects the status of the interrupt flags. TDRE 0 Description The next transmit data is in ICDR (ICDRT), or transmission cannot be started [Clearing conditions] * * * * When transmit data is written in ICDR (ICDRT) in transmission mode (TRS = 1) When a stop condition is detected in the bus line state after a stop condition is 2 issued with the I C bus format or serial format selected When a stop condition is detected with the I C bus format selected In receive mode (TRS = 0) (A 0 write to TRS during transfer is valid after reception of a frame containing an acknowledge bit) 2 (Initial value) 1 The next transmit data can be written in ICDR (ICDRT) [Setting conditions] * In transmit mode (TRS = 1), when a start condition is detected in the bus line state 2 after a start condition is issued in master mode with the I C bus format or serial format selected When data is transferred from ICDRT to ICDRS (Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is empty) In receive mode (TRS = 0), when a switch is made from slave receive mode (TRS =0) to transmit mode (TRS = 1) after detection of a start condition (first time only) * * RDRF 0 Description The data in ICDR (ICDRR ) is invalid [Clearing condition] * When ICDR (ICDRR) receive data is read in receive mode (Initial value) 1 The ICDR (ICDRR) receive data can be read [Setting condition] * When data is transferred from ICDRS to ICDRR (Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and RDRF = 0) Rev. 1.00 Jan. 29, 2008 Page 428 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14.3.2 Slave Address Register (SAR) SAR stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SAR is assigned to the same address as ICMR, and can be accessed when the ICE bit is cleared to 0 in ICCR. SAR is initialized to H'00 by a reset and in hardware standby mode. Bit 7 6 5 4 3 2 1 0 Bit Name SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Format select: Used together with the FSX bit in SARX to select the communication format. For the detail, see table 14.2. Description Slave address 6 to 0 Specifies the slave address Rev. 1.00 Jan. 29, 2008 Page 429 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14.3.3 Second Slave Address Register (SARX) SARX stores the second slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device specified by the master device. SARX is assigned to the same address as ICDR, and can be accessed only when the ICE bit is cleared to 0 in ICCR. Bit 7 6 5 4 3 2 1 0 Bit Name SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Format select: Used together with the FS bit in SAR to select the communication format. For the detail, see table 14.2. Description Slave address 6 to 0 Specifies the slave address * I2C bus format: addressing format with acknowledge bit * Synchronous serial format: non-addressing format without acknowledge bit, for master mode only Rev. 1.00 Jan. 29, 2008 Page 430 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Table 14.2 Transfer Format SAR Bit 0 FS FSX 0 SARX Bit 0 FS FSX 0 1 I2C bus format * * * 1 0 2 Operating Mode Enables the slave addresses in SAR and SARX Enables the slave address in SAR Disables the slave address in SARX Enables the slave address in SARX Disables the slave address in SAR Disables the slave addresses in SAR and SARX I2C bus format I C bus format * * 1 Clock- synchronous serial format * Rev. 1.00 Jan. 29, 2008 Page 431 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14.3.4 I2C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit 7 Bit Name MLS Initial Value R/W 0 R/W Description MSB-First/LSB-First Select 0: MSB-first 1: LSB-first Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit This bit is valid only in master mode with the I C bus format. The setting of this bit is invalid in slave mode. 0: Data and the acknowledge bit are transferred consecutively with no wait inserted. 1: After the fall of the clock for the final data bit (8th clock), the IRIC flag is set to 1 in ICCR, and a wait state begins (with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the acknowledge bit is transferred. For details, refer to section 14.4.7, IRIC Setting Timing and SCL Control. 5 4 3 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Transfer Clock Select 2 to 0 These bits are used only in master mode. These bits select the required transfer rate, together with the IICX1 (IIC_1) and IICX0 (IIC_0) bits in SCRX. Refer to table 14.3. 2 2 Rev. 1.00 Jan. 29, 2008 Page 432 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Bit 2 1 0 Bit Name BC2 BC1 BC0 Initial Value R/W 0 0 0 R/W R/W R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 when a start condition is detected. The value returns to 000 at the end of a data transfer. I C Bus Format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits 2 Clocked Synchronous Serial Mode 000: 8 bits 001: 1 bits 010: 2 bits 011: 3 bits 100: 4 bits 101: 5 bits 110: 6 bits 111: 7 bits Rev. 1.00 Jan. 29, 2008 Page 433 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Table 14.3 I2C Transfer Rate STCR Bits 5 and 6 IICX 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 5 CKS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ICMR Bit 4 CKS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 3 CKS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 Transfer Rate Clock /28 /40 /48 /64 /80 /100 /112 /128 /56 /80 /96 /128 /160 /200 /224 /256 = 5 MHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz 89.3 kHz 62.5 kHz 52.1 kHz 39.1 kHz 31.3 kHz 25.0 kHz 22.3 kHz 19.5 kHz = 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz = 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz 179 kHz 125 kHz 104 kHz 78.1 kHz 62.5 kHz 50.0 kHz 44.6 kHz 39.1 kHz = 16 MHz 517 kHz* 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz = 20 MHz 714 kHz* 500 kHz* 417 kHz* 313 kHz 250 kHz 200 kHz 179 kHz 156 kHz 357 kHz 250 kHz 208 kHz 156 kHz 125 kHz 100 kHz 89.3 kHz 78.1 kHz Note: * Outside the I C bus interface specifications (standard mode: max. 100 kHz; high-speed mode: max. 400 kHz) Rev. 1.00 Jan. 29, 2008 Page 434 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14.3.5 I2C Bus Control Register (ICCR) ICCR controls the I2C bus interface and performs interrupt flag confirmation. Bit 7 Bit Name ICE Initial Value R/W 0 R/W Description Bus Interface Enable 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized. SAR and SARX can be accessed. 1: I2C bus interface modules can perform transfer operation, and the ports function as the SCL and SDA input/output pins. ICMR and ICDR can be accessed. 6 IEIC 0 R/W I2C Bus Interface Interrupt Enable 0: Disables interrupts from the I C bus interface to the CPU 1: Enables interrupts from the I C bus interface to the CPU. 2 2 2 2 Rev. 1.00 Jan. 29, 2008 Page 435 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Bit 5 4 Bit Name MST TRS Initial Value R/W 0 0 R/W R/W Description Master/Slave Select Transmit/Receive Select 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode Both these bits will be cleared by hardware when they 2 lose in a bus contention in master mode with the I C bus 2 format. In slave receive mode with I C bus format, the R/W bit in the first frame immediately after the start condition sets these bits in receive mode or transmit mode automatically by hardware. Modification of the TRS bit during transfer is deferred until transfer is completed, and the changeover is made after completion of the transfer. [MST clearing conditions] 1. When 0 is written by software 2 2. When lost in bus contention in I C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2. When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] 1. When 0 is written by software (except for TRS setting condition 3) 2. When 0 is written in TRS after reading TRS = 1 (for TRS setting condition 3) 3 When the master device in the I2C bus format starts transmission and then fails because of a bus conflict. [TRS setting conditions] 1. When 1 is written by software (except for TRS clearing conditions 3 and 4) 2. When 1 is written in TRS after reading TRS = 0 (for TRS clearing conditions 3 and 4) 3. When 1 is received as the R/W bit after the first frame address matching in I2C bus format slave mode Rev. 1.00 Jan. 29, 2008 Page 436 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Bit 3 Bit Name ACKE Initial Value R/W 0 R/W Description Specifies whether the value of the acknowledge bit returned from the receiving device when using the I2C bus format is to be ignored and continuous transfer is performed, or transfer is to be aborted and error handling, etc., performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received acknowledge bit is not indicated by the ACKB bit, which is always 0. In this LSI, the DTC can be used to perform continuous transfer. The DTC is activated when the IRTR interrupt flag is set to 1 (IRTR is one of two interrupt flags, the other being IRIC). When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of data transmission, regardless of the value of the acknowledge bit. When the ACKE bit is 1, the TDRE, IRIC, and IRTR flags are set on completion of data transmission when the acknowledge bit is 0, and the IRIC flag alone is set on completion of data transmission when the acknowledge bit is 1. When the DTC is activated, the TDRE, IRIC, and IRTR flags are cleared to 0 after the specified number of data transfers have been executed. Consequently, interrupts are not generated during continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the ACKE bit is set to 1, the DTC is not activated and an interrupt is generated, if enabled. Depending on the receiving device, the acknowledge bit may be significant, in indicating completion of processing of the received data, for instance, or may be fixed at 1 and have no significance. Rev. 1.00 Jan. 29, 2008 Page 437 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Bit 2 0 Bit Name BBSY SCP Initial Value R/W 0 1 R/W W Description Bus Busy Start Condition/Stop Condition Prohibit In master mode: * * Writing 0 in BBSY and 0 in SCP: A stop condition is issued Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued Writing to the BBSY flag is disabled. In slave mode: * [BBSY setting condition] When the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. [BBSY clearing condition] When the SDA level changes from low to high under the condition of SCL = high, assuming that the stop condition has been issued. To issue a start/stop condition, use the MOV instruction. The I C bus interface must be set in master transmit mode before the issue of a start condition. Set MST to 1 and TRS to 1 before writing 1 in BBSY and 0 in SCP. The BBSY flag can be read to check whether the I C bus (SCL, SDA) is busy or free. The SCP bit is always read as 1. If 1 is written, the data is not stored. 2 2 Rev. 1.00 Jan. 29, 2008 Page 438 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Bit 1 Bit Name IRIC Initial Value R/W 0 Description 2 R/(W)* I2C Bus Interface Interrupt Request Flag Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR. See section 14.4.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. [Setting conditions] I C bus format master mode:* * When a start condition is detected in the bus line state after a start condition is issued (when the ICDRE flag is set to 1 because of first frame transmission)* When a wait is inserted between the data and acknowledge bit when the WAIT bit is 1 (fall of the 8th transmit/receive clock) At the end of data transfer (rise of the 9th transmit/receive clock or fall of the 8th transmit/receive clock while a wait is inserted)* When a slave address is received after bus arbitration is lost (when the AL flag is set to 1) If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) when the ACKE bit is 1* When the slave address (SVA or SVAX) matches (when the AAS or AASX flag in ICSR is set to 1) and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) When the general call address is detected (when FS=0 and the ADZ flag is set to 1) and at the end of data reception up to the subsequent retransmission start condition or stop condition detection (when the TDRE or RDRF flag is set to 1) 2 * * * * 2 I C bus format slave mode:* * * Rev. 1.00 Jan. 29, 2008 Page 439 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Bit 1 Bit Name IRIC Initial Value R/W 0 Description If 1 is received as the acknowledge bit (when the ACKB bit in ICSR is set to 1) while the ACKE bit is 1* When a stop condition is detected (when the STOP or ESTP flag in ICSR is set to 1) Clocked synchronous serial format and formatless modes: At the end of data transfer (when TDRE or RDRF flag is set to 1) When a start condition is detected with serial format selected When the TDRE or RDRF flag is set to 1 occurs other than the above conditions R/(W)* * * * * * * [Clearing conditions]* * * When 0 is written in IRIC after reading IRIC = 1* When ICDR is read from or written to by the DTC (This may not function as a clearing condition depending on the situation. For details, see the description of the DTC operation given below.) Note: * Only 0 can be written, to clear the flag. When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF flag is set, the IRTR flag may or may not be set. The IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission start 2 condition or stop condition after a slave address (SVA) or general call address match in I C bus format slave mode. Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF flag may not be set. The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous transfer using the DTC. The TDRE or RDRF flag is cleared, however, since the specified number of ICDR reads or writes have been completed. Table 14.4 shows the relationship between the flags and the transfer states. 2 Rev. 1.00 Jan. 29, 2008 Page 440 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Table 14.4 Flags and Transfer States MST TRS BBSY ESTP STOP IRTR AASX AL 1/0 1 1 1 1 0 0 0 0 0 1/0 1 1 1/0 1/0 0 0 0 0 1/0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1/0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 AAS 0 0 0 0 0 1/0 1 1 0 0 ADZ 0 0 0 0 0 1/0 0 1 0 0 ACKB State 0 0 0 0/1 0/1 0 0 0 0 0/1 Idle state (flag clearing required) Start condition issuance Start condition established Master mode wait Master mode transmit/receive end Arbitration lost SAR match by first frame in slave mode General call address match SARX match Slave mode transmit/receive end (except after SARX match) Slave mode transmit/receive end (after SARX match) Stop condition detected 0 0 0 1/0 1 1/0 1 1 0 0 0 1/0 0 0 1/0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0/1 14.3.6 I2C Bus Status Register (ICSR) ICSR consists of status flags. Rev. 1.00 Jan. 29, 2008 Page 441 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Bit 7 Bit Name ESTP Initial Value R/W 0 Description 2 R/(W)* Error Stop Condition Detection Flag This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer. [Clearing conditions] * * When 0 is written in ESTP after reading ESTP = 1 When the IRIC flag in ICCR is cleared to 0 2 6 STOP 0 R/(W)* Normal Stop Condition Detection Flag This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected after frame transfer completion. [Clearing conditions] * When 0 is written in STOP after reading STOP = 1 When the IRIC flag is cleared to 0 5 IRTR 0 R/(W)* I2C Bus Interface Continuous Transfer Interrupt Request Flag Indicates that the I2C bus interface has issued an interrupt request to the CPU, and the source is completion of reception/transmission of one frame in continuous transmission/reception for which DTC activation is possible. When the IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time. The IRTR flag is set while the TDRE or RDRF flag is set to 1. The IRTR flag is cleared by reading an existing 1 from and then writing a 0 to the flag. The IRTR flag is automatically cleared when the IRIC flag is cleared. [Setting conditions] * I C bus format slave mode: When the TDRE or RDRF flag is set to 1 with AASX = 1. * Other than I C bus format slave mode: When the TDRE or RDRF flag is set to 1 [Clearing conditions] * * When 0 is written after reading IRTR = 1 When the IRIC flag is cleared to 0 while ICE is 1 2 2 Rev. 1.00 Jan. 29, 2008 Page 442 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Bit 4 Bit Name AASX Initial Value R/W 0 Description 2 R/(W)* Second Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX. [Setting condition] * When the second slave address is detected in slave receive mode and FSX = 0 in SARX When 0 is written in AASX after reading AASX = 1 When a start condition is detected [Clearing conditions] * * 3 AL 0 * In master mode * Arbitration Lost Flag R/(W) Indicates that arbitration was lost in master mode. [Setting conditions] * * If the internal SDA and SDA pin disagree at the rise of SCL in master transmit mode If the internal SCL line is high at the fall of SCL in master transmit mode When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AL after reading AL = 1 [Clearing conditions] * * Rev. 1.00 Jan. 29, 2008 Page 443 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Bit 2 Bit Name AAS Initial Value R/W 0 Description 2 R/(W)* Slave Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. [Setting condition] * When the slave address or general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 in SAR When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in AAS after reading AAS = 1 In master mode 2 [Clearing conditions] * * * 1 ADZ 0 R/(W)* General Call Address Recognition Flag In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition is the general call address (H'00). To clear the ADZ flag, read a 1 from and then write a 0 to it. This flag is automatically reset when ICDR is written to (during transmission) or read from (during reception). [Setting condition] * When the general call address (one frame including a R/W bit is H'00) is detected in slave receive mode and FS = 0 When ICDR is written to (transmit mode) or read from (receive mode) When 0 is written in ADZ after reading ADZ = 1* [Clearing conditions] * * In master mode Rev. 1.00 Jan. 29, 2008 Page 444 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Bit 0 Bit Name ACKB Initial Value R/W 0 R/W Description Acknowledge Bit Stores acknowledge data. Transmit mode: [Setting condition] * * * * When 1 is received as the acknowledge bit when ACKE=1 in transmit mode [Clearing conditions] When 0 is received as the acknowledge bit when ACKE=1 in transmit mode When 0 is written to the ACKE bit Receive mode: 0: Returns 0 as acknowledge data after data reception 1: Returns 1 as acknowledge data after data reception When this bit is read, the value loaded from the bus line (returned by the receiving device) is read in transmission (when TRS = 1). In reception (when TRS = 0), the value set by internal software is read. When this bit is written, acknowledge data that is returned after receiving is rewritten regardless of the TRS value. The value loaded from the receiving device is retained. Therefore, care must be taken when rewriting the register using bit-manipulation instructions. Note: * Only 0 can be written to clear the flag. Rev. 1.00 Jan. 29, 2008 Page 445 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14.3.7 Serial Control Register X (SCRX) SCRX controls register access, the I2C interface operating mode. Bit 7 6 5 Bit Name IICX1 IICX0 Initial Value R/W 0 0 0 R/W R/W R/W Description These bits are reserved and always return 0 when read, and should only be written with 0. I C transfer-rate select 1 and 0 Along with bits CKS2 to CKS0 of ICMR, this bit selects the transfer rate in the master mode. For details on setting the transfer rate, refer to table 14.3 I C master enable This bit controls access by the CPU to the data register and control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR) of the I C bus interface. 0: Disables CPU access to the data register and control registers of the I2C bus interface. 1: Enables CPU access to the data register and control registers of the I C bus interface. 3 1 All 0 R R/W Reserved This bit is always read as 1. 2 to 0 Reserved This bit should not be written with 0 2 2 2 2 4 IICE 0 R/W Rev. 1.00 Jan. 29, 2008 Page 446 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14.3.8 DDC Switch Register (DDCSWR) DDCSWR controls IIC internal latch clearance. Bit 7 to 4 3 2 1 0 CLR3 CLR2 CLR1 CLR0 Bit Name Initial Value R/W All 0 1 1 1 1 2 W* Description Reserved. Only 0 can be written. IIC Clear 3 to 0 Controls initialization of the internal state of IIC_0 and IIC_1. 00--: Setting prohibited 0100: Setting prohibited 0101: IIC_0 internal latch cleared 0110: IIC_1 internal latch cleared 0111: IIC_0 and IIC_1 internal latches cleared 1---: Invalid setting When a write operation is performed on these bits, a clear signal is generated for the internal latch circuit of the corresponding module, and the internal state of the IIC module is initialized. These bits can only be written to; they are always read as 1. Write data to this bit is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. When clearing is required again, all the bits must be written to in accordance with the setting. If the function of these bits is not used, set all of the CLR3 to CLR0 bits to 1 when writing to DDCSWR. W*2 W*2 W*2 Notes: 1. Only 0 can be written, to clear the flag. 2. This bit is always read as 1. Rev. 1.00 Jan. 29, 2008 Page 447 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14.4 14.4.1 Operation I2C Bus Data Format The I2C bus interface has serial and I2C bus formats. The I2C bus formats are addressing formats with an acknowledge bit. These are shown in figures 15-3 (a) and (b). The first frame following a start condition always consists of 8 bits. The serial format is a non-addressing format with no acknowledge bit. Although start and stop conditions must be issued, this format can be used as a synchronous serial format. This is shown in figure 14.4. Figure 14.5 shows the I2C bus timing. The symbols used in figures 15-3 to 15-5 are explained in table 14.5. (a) I2C bus format (FS = 0 or FSX = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) (b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1 n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) Figure 14.3 I2C Bus Data Formats (I2C Bus Formats) Rev. 1.00 Jan. 29, 2008 Page 448 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 FS = 1 and FSX = 1 S 1 DATA 8 1 DATA n m P 1 n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) Figure 14.4 I2C Bus Data Format (Serial Format) SDA SCL S 1-7 SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A/A P Figure 14.5 I2C Bus Timing Table 14.5 I2C Bus Data Format Symbols Legend S SLA R/W A DATA P Start condition. The master device drives SDA from high to low while SCL is high Slave address, by which the master device selects a slave device Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 Acknowledge. The receiving device (the slave in master transmit mode, or the master in master receive mode) drives SDA low to acknowledge a transfer Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or LSB-first format is selected by bit MLS in ICMR Stop condition. The master device drives SDA from low to high while SCL is high Rev. 1.00 Jan. 29, 2008 Page 449 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14.4.2 Initial Setting At startup the following procedure is used to initialize the IIC. Start initialization Set MSTP4 = 0 (IIC_0) MSTP3 = 0 (IIC_1) (MSTPCRB) Set IICE = 1 (SCRX) Set ICE = 0 (ICCR) Set SAR and SARX Set ICE = 1 (ICCR) Set ICSR Set SCRX Set IMCR Set ICCR Transmit/receive start Clear module stop Enable CPU access by IIC control register and data register Enable SAR and SARX access Set transfer format for 1st slave address, 2nd slave address, and IIC (SVA8-SVA0, FS, SVAX6-SVAX0, FSX) Enable IMCR and IMDR access. Use SCL and SDA pins is IIC port Set acknowledge bit (ACKB) Set transfer rate (IICX) Set transfer format, wait insertion, and transfer rate (MLS, WAIT, CKS2-CKS0) Set interrupt enable, transfer mode, and acknowledge judgment (IEIC, MST, TRS, ACKE) Figure 14.6 Flowchart for IIC Initialization (Example) Note: The ICMR register should be written to only after transmit or receive operations have completed. Writing to the ICMR register while a transmit or receive operation is in progress could cause an erroneous value to be written to bit counter bits BC2 to BC0. This could result in improper operation. Rev. 1.00 Jan. 29, 2008 Page 450 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14.4.3 Master Transmit Operation In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. Figure 14.7 is a flowchart showing an example of the master transmit mode. Rev. 1.00 Jan. 29, 2008 Page 451 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Start Initial settings [1] Initial settings Read BBSY flag in ICCR [2] Determine status of SCL and SDA lines No BBSY = 0? Yes Set MST = 1 and TRS = 1 (ICCR) Write BBSY = 1 and SCP = 0 (ICCR) [3] Set to master transmit mode [4] Generate start condition Read IRIC flag in ICCR [5] Wait for start condition to be met No IRIC = 1? Yes Write transmit data to ICDR Clear IRIC flag in ICCR [6] Set 1st byte (slave address + R/W) transmit data (Perform ICDR write and IRIC flag clear operations continuously) Read IRIC flag in ICCR [7] Wait for end of 1 byte transmission No IRIC = 1? Yes Read ACKB bit in ICSR ACKB = 0? Yes Transmit mode? Yes Write transmit data to ICDR Clear IRIC flag in ICCR [9] Set transmit data for 2nd byte onward (Perform ICDR write and IRIC flag clear operations continuously) No Master receive mode No [8] Judge acknowledge signal from specified slave device Read IRIC flag in ICCR [10] Wait for end of 1 byte transmission No IRIC = 1? Yes Read ACKB bit in ICSR [11] Judge end of transmission No Transmit complete? (ACKB = 1?) Yes Clear IRIC flag in ICCR [12] Generate stop condition. Write BBSY = 0 and SCP = 0 (ICCR) End Figure 14.7 Flowchart for Master Transmit Mode (Example) Rev. 1.00 Jan. 29, 2008 Page 452 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 The procedure for transmitting data sequentially, synchronized with ICDR (ICDRT) write operations, is described below. Perform initial settings as described in section 14.4.2, Initial Setting. Read the BBSY flag in ICCR to confirm that the bus is free. Set bits MST and TSR in ICCR to 1 to switch to the master transmit mode. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is high, and generates the start condition. 5. The IRIC and IRTR flags are set to 1 when the start condition is generated. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. 6. After the start condition is detected, write the data (slave address + R/W) to ICDR. With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates the 7-bit slave address and transmit/receive direction (R/W). Next, clear the IRIC flag to 0 to indicate the end of the transfer. Continue successively writing to ICDR and clearing the IRIC flag to ensure that processing of other interrupts does not intervene. If the time required to transmit one byte of data elapses by the time the IRIC flag is cleared, it will not be possible to determine the end of the transmission. The master device sequentially sends the transmit clock and the data written to ICDR. The selected slave device (i.e., the slave device with the matching slave address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal. 7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 8. Read the ACKB bit in ICSR to confirm that its value is 0. If the slave device has not returned an acknowledge signal and the value of ACKB is 1, perform the transmit end processing described in step.12 and then recommence the transmit operation from the beginning. 9. Write the transmit data to ICDR. Next, clear the IRIC flag to 0 to indicate the end of the transfer. Then continue successively writing to ICDR and clearing the IRIC flag as described in step.6. Transmission of the next frame is synchronized with the internal clock. 10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in synchronization with the internal clock until the next transmit data is written. 11. Read the ACKB bit in ICSR to confirm that the slave device has returned an acknowledge signal and the value of ACKB is 0. If the slave device has not returned an acknowledge signal and the value of ACKB is 1, perform the transmit end processing described in step.12. 12. Clear the IRIC flag to 0. Write 0 to the ACKE bit in ICCR and clear the received ACKB bit to 0. 1. 2. 3. 4. Rev. 1.00 Jan. 29, 2008 Page 453 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Generate start condition SCL (Master output) SDA (Master output) SDA (Slave output) ICDRE IRIC IRTR ICDRT ICDRS Note: ICDR data setting timing Normal operation Improper operation will result User processing [4] Write BBSY = 1 and SCP = 0 (generate start condition) [6] ICDR write [6] IRIC clearance [9] ICDR write [9] IRIC clearance Address + R/W Address + R/W Data 1 Data 1 Interrupt request Interrupt request 1 Bit 7 2 Bit 6 3 Bit 5 4 Bit 4 5 Bit 3 6 Bit 2 7 Bit 1 8 Bit 0 R/W [7] A 9 1 Bit 7 2 Bit 6 Slave address [5] Data 1 Figure 14.8 (1) Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0) Rev. 1.00 Jan. 29, 2008 Page 454 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Generate start condition SCL (Master output) SDA (Master output) 8 Bit 0 Data 1 SDA (Slave output) ICDRE IRIC IRTR ICDR Data 1 Data 2 [7] A 9 1 Bit 7 2 3 4 Bit 4 5 Bit 3 6 Bit 2 7 8 9 Bit 6 Bit 5 Bit 1 Bit 0 [10] A Data 2 User processing [9] ICDR write [9] IRIC clearance [11] ACKB read [12] Write BBSY = 0 and SCP = 0 (generate stop condition) [12] IRIC clearance Figure 14.8 (2) Example of Master Transmit Mode Stop Condition Generation Timing (MLS = WAIT = 0) 14.4.4 Master Receive Operation In I2C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits the data containing the slave address + R/W (0: read) in the 1st frame after a start condition is generated in the master transmit mode. After the slave device is selected the switch to receive operation takes place. (1) Receive Operation Using Wait States Figures 14-9 (1) and 14-9 (2) are flowcharts showing examples of the master receive mode (WAIT = 1). Rev. 1.00 Jan. 29, 2008 Page 455 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Master receive mode Set TRS = 0 (ICCR) Set ACKB = 0 (ICSR) Clear IRIC flag in ICCR Set WAIT = 1 (ICMR) Read ICDR [2] Receive start, dummy read [1] Set to receive mode Read IRIC flag in ICCR No IRIC = 1? Yes No IRTR = 1? Yes Final receive? No Read ICDR Clear IRIC flag in ICCR Yes [3] Receive wait state (IRIC set at falling edge of 8th clock cycle) or Wait for end of reception of 1 byte (IRIC set at rising edge of 9th clock cycle) [4] Data receive completed judgment [5] Read receive data [6] Clear IRIC flag (cancel wait state) Set ACKB = 1 (ICSR) 1 clock cycle wait state Set TRS = 1 (ICCR) Read ICDR Clear IRIC flag in ICCR [7] Set acknowledge data for final receive [8] Wait time until TRS setting [9] Set TRS to generate stop condition [10] Read receive data [11] Clear IRIC flag (cancel wait state) Read IRIC flag in ICCR No IRIC = 1? Yes IRTR = 1? No Clear IRIC flag in ICCR Yes [12] Receive wait state (IRIC set at falling edge of 8th clock cycle) or Wait for end of reception of 1 byte (IRIC set at rising edge of 9th clock cycle) [13] Data receive completed judgment [14] Clear IRIC flag (cancel wait state) Set WAIT = 0 (ICMR) Clear IRIC flag in ICCR Read ICDR Write BBSY = 0 and SCP = 0 (ICCR) End [15] Cancel wait mode Clear IRIC flag (IRIC flag should be cleared when WAIT = 0) [16] Read final receive data [17] Generate stop condition Figure 14.9 (1) Flowchart for Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1) (Example) Rev. 1.00 Jan. 29, 2008 Page 456 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Master receive mode Set TRS = 0 (ICCR) Set ACKB = 0 (ICSR) [1] Clear IRIC flag in ICCR Set WAIT = 1 (ICMR) Read ICDR [2] Receive start, dummy read Set to receive mode Read IRIC flag in ICCR No IRIC = 1? Yes Set ACKB = 1 (ICSR) Set TRS = 1 (ICCR) Clear IRIC flag in ICCR [3] Receive wait state (IRIC set at falling edge of 8th clock cycle) or Wait for end of reception of 1 byte (IRIC set at rising edge of 9th clock cycle) [7] [9] Set acknowledge data for final receive Set TRS to generate stop condition [11] Clear IRIC flag (cancel wait state) Read IRIC flag in ICCR No [12] Wait for end of reception of 1 byte (IRIC set at rising edge of 9th clock cycle) IRIC = 1? Yes Set WAIT = 0 (ICMR) Clear IRIC flag in ICCR Read ICDR Write BBSY = 0 and SCP = 0 (ICCR) End [15] Cancel wait mode Clear IRIC flag (IRIC flag should be cleared when WAIT = 0) [16] Read final receive data [17] Generate stop condition Figure 14.9 (2) Flowchart for Master Receive Mode (Receiving 1 Byte) (WAIT = 1) (Example) The procedure for receiving data sequentially, using the wait states (WAIT bit) for synchronization with ICDR (ICDRR) read operations, is described below. The procedure below describes the operation for receiving multiple bytes. Note that some of the steps are omitted when receiving only 1 byte. Refer to figure 14.9 (2) for details. Rev. 1.00 Jan. 29, 2008 Page 457 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Clear the IRIC flag to 0, then set the WAIT bit in ICMR to 1. 2. When ICDR is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. 3. The IRIC flag is set to 1 by the following two conditions. At that point, an interrupt request is issued to the CPU if the IEIC bit in ICCR is set to 1. The flag is set at the falling edge of the 8th clock cycle of the receive clock for 1 frame. SCL is automatically held low, in synchronization with the internal clock, until the IRIC flag is cleared. The flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame. The IRIC flag and ICDRF flag are set to 1, indicating that reception of 1 frame of data has ended. The master device continues to output the receive clock for the receive data. 4. Read the IRTR flag in ICSR. If the IRTR flag value is 0, the wait state is cancelled by clearing the IRIC flag as described in step.6 below. If the IRTR flag value is 1 and the next receive data is the final receive data, perform the end processing described in step.7 below. 5. If the IRTR flag value is 1, read the ICDR receive data. 6. Clear the IRTR flag to 0. If condition described in step.3-1 is true, the master device drives SDA to low level and returns an acknowledge signal when the receive clock outputs the 9th clock cycle. Further data can be received by repeating steps.3 through 6. 7. Set the ACKB bit in ICSR to 1 to set the acknowledge data for the final receive. 8. Wait for at least 1 clock cycle after the IRIC flag is set to 1 and then wait for the rising edge of the 1st clock cycle of the next receive data. 9. Set the TSR bit in ICCR to 1 to switch from the receive mode to the transmit mode. The TSR bit setting value at this point becomes valid when the rising edge of the next 9th clock cycle is input. 10. Read the ICDR receive data. 11. Clear the IRTR flag to 0. 12. The IRIC flag is set to 1 by the following two conditions. The flag is set at the falling edge of the 8th clock cycle of the receive clock for 1 frame. SCL is automatically held low, in synchronization with the internal clock, until the IRIC flag is cleared. The flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame. The IRIC flag and ICDRF flag are set to 1, indicating that reception of 1 frame of data has ended. The master device continues to output the receive clock for the receive data. Rev. 1.00 Jan. 29, 2008 Page 458 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 13. Read the IRTR flag in ICSR. If the IRTR flag value is 0, the wait state is cancelled by clearing the IRIC flag as described in step.14 below. If the IRTR flag value is 1 and the receive operation has finished, perform the issue stop condition processing described in step.15 below. 14. If the IRTR flag value is 0, clear the IRIC flag to 0 to cancel the wait state. Return to reading the IRIC flag, as described in step.12, to detect the end of the receive operation. 15. Clear the WAIT bit in ICMR to 0 to cancel the wait mode. Then clear the IRIC flag to 0. The IRIC flag should be cleared when the value of WAIT is 0 (The stop condition may not be output properly when the issue stop condition instruction is executed if the WAIT bit was cleared to 0 after the IRIC flag is cleared to 0). 16. Read the final receive data in ICDR. 17. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. Master transmit mode SCL (master output) SDA (slave output) Master receive mode 9 A 1 2 3 4 5 6 7 8 9 1 2 3 4 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Data 1 Bit 1 Bit 0 [3] A [3] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Data 2 SDA (master output) IRIC IRTR ICDR [4] IRTR = 0 [4] IRTR = 1 Data 1 User processing [2] ICDR read (dummy read) [1] TRS cleared to 0 IRIC clearance [6] IRIC clearance (cancel wait) [5] ICDR read (data 1) [6] IRIC clearance Figure 14.10 (1) Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1) Rev. 1.00 Jan. 29, 2008 Page 459 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 [8] 1 clock cycle wait time SCL (master output) Stop condition generated 4 5 6 7 8 9 8 9 1 2 3 SDA Bit 0 (slave output) Data 2 [3] SDA (master output) IRIC IRTR ICDR [4] IRTR = 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 [3] A Data 3 Bit 1 Bit 0 [12] A [12] [4] IRTR = 1 [13] IRTR = 0 [13] IRTR = 1 Data 1 Data 2 Data 3 User processing [6] IRIC clearance [11] IRIC clearance [10] ICDR read (data 2) [9] TRS set to 1 [14] IRIC clearance [15] WAIT cleared to 0 IRIC clearance [17] Stop condition issued [7] ACKB set to 1 [16] ICDR read (data 3) Figure 14.10 (2) Example of Master Receive Mode Stop Condition Generation Timing (MLS = ACKB = 0, WAIT = 1) 14.4.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The slave device compares its own address with the slave address in the first frame following the establishment of the start condition issued by the master device. If the addresses match, the slave device operates as the slave device designated by the master device. Figure 14.14 is a flowchart showing an example of slave receive mode operation. Rev. 1.00 Jan. 29, 2008 Page 460 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Start Initialize Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR Read IRIC in ICCR No [2] IRIC = 1? Yes [1] Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? Yes Read TRS in ICCR TRS = 0? Yes Last receive? No Read ICDR Clear IRIC in ICCR Yes No Slave transmit mode No General call address processing * Description omitted [3] [1] Select slave receive mode [2] Wait for the first byte to be received (slave address) [3] Start receiving. The first read is a dummy read [4] Read IRIC in ICCR No IRIC = 1? Yes [4] Wait for the transfer to end [5] Set acknowledge data for the last receive [6] Start the last receive [7] Wait for the transfer to end Set ACKB = 0 in ICSR Read ICDR Clear IRIC in ICCR [5] [6] [8] Read the last receive data Read IRIC in ICCR No IRIC = 1? Yes Read ICDR Clear IRIC in ICCR End [7] [8] Figure 14.11 Flowcharts for Slave Transmit Mode (Example) Rev. 1.00 Jan. 29, 2008 Page 461 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. 2. When the start condition output by the master device is detected, the BBSY flag in ICCR is set to 1. 3. When the slave address matches in the first frame following the start condition, the device operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the TRS bit in ICCR remains cleared to 0, and slave receive operation is performed. 4. At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag has been set to 1, the slave device drives SCL low from the fall of the receive clock until data is read into ICDR. 5. Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0. Receive operations can be performed continuously by repeating steps 4 and 5. When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. Rev. 1.00 Jan. 29, 2008 Page 462 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Start condition issuance SCL (master output) SCL (slave output) SDA (master output) SDA (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 1 2 3 4 5 6 7 8 9 1 2 Slave address R/W [4] A Data 1 RDRF IRIC Interrupt request generation Address + R/W ICDRS ICDRR Address + R/W User processing [5] ICDR read [5] IRIC clearance Figure 14.12 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) Rev. 1.00 Jan. 29, 2008 Page 463 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 SCL (master output) SCL (slave output) SDA (master output) 7 8 9 1 2 3 4 5 6 7 8 9 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 1 SDA (slave output) [4] Data 2 [4] A A RDRF IRIC Interrupt request generation Data 1 Data 2 Interrupt request generation ICDRS ICDRR Data 1 Data 2 User processing [5] ICDR read [5] IRIC clearance Figure 14.13 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) 14.4.6 Slave Transmit Operation In slave transmit operation, the slave device compares its own address with the slave address transmitted by the master device in the first frame (address receive frame) following detection of the start condition. If the addresses match and the 8th bit (R/W) is set to 1 (read), the TRS bit in ICCR is automatically set to 1 and slave transmit mode is activated. Figure 14.17 is a flowchart showing an example of slave transmit mode operation. Rev. 1.00 Jan. 29, 2008 Page 464 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Slave transmit mode Clear IRIC in ICCR [1] Set transmit data for the second and subsequent bytes [1] [2] Wait for 1 byte to be transmitted [3] Test for end of transfer Clear IRIC in ICCR [4] Select slave receive mode [5] Dummy read (to release the SCL line) Read IRIC in ICCR No [2] IRIC = 1? Yes Read ACKB in ICSR End of transmission (ACKB = 1)? Yes Set TRS = 0 in ICCR Read ICDR Clear IRIC in ICCR [4] [3] Write transmit data in ICDR No [5] End Figure 14.14 Flowcharts for Slave Receive Mode (Example) In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode. 2. When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to Rev. 1.00 Jan. 29, 2008 Page 465 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 1, and the mode changes to slave transmit mode automatically. The TDRF flag is set to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is written. 3. After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0. The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The slave device sequentially sends the data written into ICDR in accordance with the clock output by the master device at the timing shown in figure 14.18. 4. When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device drives SCL low from the fall of the transmit clock until data is written to ICDR. The master device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine whether the transfer operation was performed normally. When the TDRE internal flag is 0, the data written into ICDR is transferred to ICDRS, transmission is started, and the TDRE internal flag and the IRIC and IRTR flags are set to 1 again. 5. To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted into ICDR. The TDRE flag is cleared to 0. Transmit operations can be performed continuously by repeating steps 4 and 5. To end transmission, write H'FF to ICDR to release SDA on the slave side. When SDA is changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is cleared to 0. Rev. 1.00 Jan. 29, 2008 Page 466 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Slave receive mode SCL (master output) SDA (slave output) Slave transmit mode 8 9 1 2 3 4 5 6 7 8 9 1 2 SDA (slave output) SDA (slave output) R/W A [2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Data 1 A Data 2 TDRE [4] IRIC Interrupt request generation Interrupt request generation Interrupt request generation ICDRT Data 1 Data 2 ICDRS Data 1 Data 2 User processing [3] IRIC clearance [3] ICDR write [3] ICDR write [5] IRIC clearance [3] ICDR write Figure 14.15 Example of Slave Transmit Mode Operation Timing (MLS = 0) Rev. 1.00 Jan. 29, 2008 Page 467 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 14.19 shows the IRIC set timing and SCL control. (a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait) SCL 7 8 9 1 SDA IRIC 7 8 A 1 User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) (b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL 8 9 1 SDA IRIC 8 A 1 User processing Clear IRIC Clear Write to ICDR (transmit) IRIC or read ICDR (receive) (c) When FS = 1 and FSX = 1 (synchronous serial format) SCL 7 8 1 SDA IRIC 7 8 1 User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) Figure 14.16 IRIC Setting Timing and SCL Control Rev. 1.00 Jan. 29, 2008 Page 468 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14.4.8 Operation Using the DTC The I2C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in conjunction with CPU processing by means of interrupts. Table 14.5 shows some examples of processing using the DTC. These examples assume that the number of transfer data bytes is known in slave mode. Table 14.6 Examples of Operation Using the DTC Item Master Transmit Mode Master Receive Mode Transmission by CPU (ICDR write) Slave Transmit Mode Reception by CPU (ICDR read) Slave Receive Mode Reception by CPU (ICDR read) Slave address + Transmission by R/W bit DTC (ICDR write) transmission/ reception Dummy data read Actual data transmission/ reception Dummy data (H'FF) write Last frame processing Transfer request processing after last frame processing Setting of number of DTC transfer data frames -- Transmission by DTC (ICDR write) -- Not necessary 1st time: Clearing by CPU 2nd time: End condition issuance by CPU Processing by CPU (ICDR read) Reception by DTC (ICDR read) -- Reception by CPU (ICDR read) Not necessary -- Transmission by DTC (ICDR write) Processing by DTC (ICDR write) Not necessary -- Reception by DTC (ICDR read) -- Reception by CPU (ICDR read) Automatic clearing Not necessary on detection of end condition during transmission of dummy data (H'FF) Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to dummy data (H'FF)) Transmission: Reception: Actual Actual data count data count + 1 (+1 equivalent to slave address + R/W bits) Rev. 1.00 Jan. 29, 2008 Page 469 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14.4.9 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 14.20 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D Latch Q D C Q Latch Match detector Internal SCL or SDA signal System clock period Sampling clock Figure 14.17 Block Diagram of Noise Canceler 14.4.10 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed by (1) setting bits CLR3 to CLR0 in the DDCSWR register or (2) clearing the ICE bit. For details of settings for bits CLR3 to CLR0, see section 14.3.8, DDC Switch Register (DDCSWR). Scope of Initialization: The initialization executed by this function covers the following items: * TDRE and RDRF internal flags * Transmit/receive sequencer and internal operating clock counter Rev. 1.00 Jan. 29, 2008 Page 470 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 * Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data output, etc.) The following items are not initialized: * Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, and STCR) * Internal latches used to retain register read information for setting/clearing flags in the ICMR, ICCR, ICSR, and DDCSWR registers * The value of the ICMR register bit counter (BC2 to BC0) * Generated interrupt sources (interrupt sources transferred to the interrupt controller) Notes on Initialization: * Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. * Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary. * When initialization is performed by means of the DDCSWR register, the write data for bits CLR3 to CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. Similarly, when clearing is required again, all the bits must be written to simultaneously in accordance with the setting. * If a flag clearing setting is made during transmission/reception, the IIC module will stop transmitting/receiving at that point and the SCL and SDA pins will be released. When transmission/reception is started again, register initialization, etc., must be carried out as necessary to enable correct communication as a system. The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0, or according to the ICE bit. 2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBST bit to 0, and wait for two transfer rate clock cycles. Rev. 1.00 Jan. 29, 2008 Page 471 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0, or according to the ICE bit. 4. Initialize (re-set) the IIC registers. 14.5 Usage Notes 1. In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition. Note that SCL may not yet have gone low when BBSY is cleared to 0. 2. Either of the following two conditions will start the next transfer. Pay attention to these conditions when reading or writing to ICDR. Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to ICDRS) Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to ICDRR) 3. Table 14.7 shows the timing of SCL and SDA output in synchronization with the internal clock. Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance, series resistance, and parallel resistance. Table 14.7 I2C Bus Timing (SCL and SDA Output) Item SCL output cycle time SCL output high pulse width SCL output low pulse width SDA output bus free time Start condition output hold time Retransmission start condition output setup time Stop condition output setup time Data output setup time (master) Data output setup time (slave) Data output hold time tSDAHO Symbol tSCLO tSCLHO tSCLLO tBUFO tSTAHO tSTASO tSTOSO tSDASO Output Timing 28 tcyc to 256 tcyc 0.5 tSCLO 0.5 tSCLO 0.5 tSCLO - 1 tcyc 0.5 tSCLO - 1 tcyc 1 tSCLO 0.5 tSCLO + 2 tcyc 1 tSCLLO - 3 tcyc 1 tSCLL - 3 tcyc 3 tcyc ns Unit ns ns ns ns ns ns ns ns Notes Figure 23-20 (reference) Rev. 1.00 Jan. 29, 2008 Page 472 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 4. SCL and SDA input is sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in table 23-9 in section 23, Electrical Characteristics. Note that the I2C bus interface AC timing specifications will not be met with a system clock frequency of less than 5 MHz. 5. The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time does not exceed the values given in the table 14.8. Table 14.8 Permissible SCL Rise Time (tSr) Values Time Indication tcyc IICX Indication 0 7.5 tcyc Standard mode High-speed mode 1 17.5 tcyc Standard mode High-speed mode I C Bus Specification = (Max.) 5 MHz 1000 ns 300 ns 1000 ns 300 ns 1000 ns 300 ns 1000 ns 300 ns 2 = 8 MHz 937 ns 300 ns 1000 ns 300 ns = 10 MHz 750 ns 300 ns 1000 ns 300 ns = = 16 MHz 20 MHz 468 ns 300 ns 375 ns 300 ns 1000 ns 875 ns 300 ns 300 ns Rev. 1.00 Jan. 29, 2008 Page 473 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 6. The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tScyc and tcyc, as shown in table 14.7. However, because of the rise and fall times, the I2C bus interface specifications may not be satisfied at the maximum transfer rate. Table 14.9 shows output timing calculations for different operating frequencies, including the worst-case influence of rise and fall times. tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 s) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input timing permits this output timing for use as slave devices connected to the I2C bus. Rev. 1.00 Jan. 29, 2008 Page 474 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Table 14.9 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] I C Bus SpecifitSr/tSf Influence cation (Min.) (Max.) Standard mode -1000 4000 600 4700 1300 4700 1300 4000 600 4700 600 4000 600 250 100 250 100 2 Item tSCLHO tcyc Indication 0.5 tSCLO (-tSr) = 5 MHz 4000 950 4750 1000* 3800* 750* 1 1 = 8 MHz 4000 950 4750 1000* 3875* 825* 1 1 = 10 MHz 4000 950 4750 1000* 3900* 850* 1 1 = 16 MHz 4000 950 4750 1000* 3938* 888* 1 1 = 20 MHz 4000 950 4750 1000* 3950* 900* 1 1 High-speed -300 mode tSCLLO 0.5 tSCLO (-tSf ) Standard mode -250 High-speed -250 mode tBUFO 0.5 tSCLO - 1 tcyc ( -tSr ) Standard mode -1000 1 1 1 1 1 High-speed -300 mode Standard mode -250 tSTAHO 0.5 tSCLO - 1 tcyc (-tSf ) 4550 800 9000 2200 4400 1350 3100 400 3100 400 4625 875 9000 2200 4250 1200 3325 625 3325 625 4650 900 9000 2200 4200 1150 3400 700 3400 700 4688 938 9000 2200 4125 1075 3513 813 3513 813 4700 950 9000 2200 4100 1050 3550 850 3550 850 High-speed -250 mode Standard mode -1000 tSTASO 1 tSCLO (-tSr ) High-speed -300 mode tSTOSO 0.5 tSCLO + 2 tcyc (-tSr ) Standard mode -1000 High-speed -300 mode 2 -1000 1 tSCLLO* -3 Standard (master) tcyc mode (-tSr ) High-speed -300 mode tSDASO 2 1 tSCLL* - *2 (slave) 3 tcyc (-tSr ) tSDASO Standard mode -1000 High-speed -300 mode Rev. 1.00 Jan. 29, 2008 Page 475 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Time Indication (at Maximum Transfer Rate) [ns] tSr/tSf Influence (Max.) Standard mode 0 I C Bus Specification (Min.) 0 0 2 Item tSDAHO tcyc Indication 3 tcyc = 5 MHz 600 600 = 8 MHz 375 375 = 10 MHz 300 300 = 16 MHz 188 188 = 20 MHz 150 150 High-speed 0 mode Notes: 1. Does not meet the I2C bus interface specification. Remedial action such as the following is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate; (d) select slave devices whose input timing permits this output timing. The values in the above table will vary depending on the settings of the IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the 2 maximum transfer rate; therefore, whether or not the I C bus interface specifications are met must be determined in accordance with the actual setting conditions. 2 2. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.). 7. Note on ICDR Read at End of Master Reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR, and so it will not be possible to read the second byte of data. If it is necessary to read the second byte of data, issue the stop condition in master receive mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the bus has been released, then read the ICDR register with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the interval between execution of the instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the actual generation of the stop condition, the clock may not be output correctly in subsequent master transmission. Clearing of the MST bit after completion of master transmission/reception, or other modifications of IIC control bits to change the transmit/receive operating mode or settings, must be carried out during interval (a) in figure 14.18 (after confirming that the BBSY bit has been cleared to 0 in the ICCR register). Rev. 1.00 Jan. 29, 2008 Page 476 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 Stop condition (a) SDA SCL Internal clock BBSY bit Master receive mode ICDR reading prohibited Bit 0 8 A 9 Start condition Execution of stop condition issuance instruction (0 written to BBSY and SCP) Confirmation of stop condition generation (0 read from BBSY) Start condition issuance Figure 14.18 Points for Attention Concerning Reading of Master Receive Data 8. Notes on Start Condition Issuance for Retransmission Figure 14.19 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. Rev. 1.00 Jan. 29, 2008 Page 477 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 [1] Wait for end of 1-byte transfer IRIC = 1 ? Yes Clear IRIC in ICSR Start condition issuance? Yes Read SCL pin SCL = Low ? Yes Write BBSY = 1, SCP = 0 (ICSR) Read SCL pin SCL = High ? Yes Write transmit data to ICDR [5] No [4] [3] No [2] No Other processing [5] Set transmit data (slave address + R/W) Note: Program so that processing from [3] to [5] is executed continuously. No [1] [2] Determine whether SCL is low [3] Issue restart condition instruction for retransmission [4] Determine whether SCL is high SCL SDA ACK Start condition (retransmission) Bit 7 IRIC [1] IRIC determination [2] Determination of SCL = low [4] Determination of SCL = high [5] ICDR write [3] Start condition instruction issuance Figure 14.19 Flowcharts and Timing of Start Condition Instruction Issuance for Retransmission Rev. 1.00 Jan. 29, 2008 Page 478 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 9. Notes on I2C Bus Interface Stop Condition Instruction Issuance If the rise time of the 9th SCL acknowledge exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, issue the stop condition instruction after reading SCL and determining it to be low, as shown below. 9th clock VIH High period secured SCL As waveform rise is late, SCL is detected as low SDA Stop condition IRIC [1] Determination of SCL = low [2] Stop condition instruction issuance Figure 14.20 Timing of Stop Condition Issuance 10. Notes on IRIC Flag Clearance when Using Wait Function If the SCL rise time exceeds the designated duration or if the slave device is of the type that keeps SCL low and applies a wait state when the wait function is used in the master mode of the I2C bus interface, read SCL and clear the IRIC flag after determining that SCL has gone low, as shown below. Clearing the IRIC flag to 0 when WAIT is set to 1 and SCL is being held at high level can cause the SDA value to change before SCL goes low, resulting in a start condition or stop condition being generated erroneously. SCL = high duration maintained SCL VIH SCL = low detected SDA IRIC [1] Judgement that SCL = low [2] IRIC clearance Figure 14.21 IRIC Flag Clearance in WAIT = 1 Status Rev. 1.00 Jan. 29, 2008 Page 479 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 11. Notes on ICDR Reads and ICCR Access in Slave Transmit Mode In a transmit operation in the slave mode of the I2C bus interface, do not read the ICDR register or read or write to the ICCR register during the period indicated by the shaded portion in figure 14.22. Normally, when interrupt processing is triggered in synchronization with the rising edge of the 9th clock cycle, the period in question has already elapsed when the transition to interrupt processing takes place, so there is no problem with reading the ICDR register or reading or writing to the ICCR register. To ensure that the interrupt processing is performed properly, one of the following two conditions should be applied. (a) Make sure that reading received data from the ICDR register, or reading or writing to the ICCR register, is completed before the next slave address receive operation starts. (b) Monitor the BC2 to BC0 counter in the ICMR register and, when the value of BC2 to BC0 is 000 (8th or 9th clock cycle), allow a waiting time of at least 2 transfer clock cycles in order to involve the problem period in question before reading from the ICDR register, or reading or writing to the ICCR register. Waveforms if problem occurs SDA SCL TRS R/W 8 Address received Period when ICDR reads and ICCR reads and writes are prohibited (6 system clock cycles) A 9 Data transmission ICDR write Bit 7 Detection of 9th clock cycle rising edge Figure 14.22 ICDR Read and ICCR Access Timing in Slave Transmit Mode 12. Notes on TRS Bit Setting in Slave Mode From the detection of the rising edge of the 9th clock cycle or of a stop condition to when the rising edge of the next SCL pin signal is detected (the period indicated as (a) in figure 14.23) in the slave mode of the I2C bus interface, the value set in the TRS bit in the ICCR register is effective immediately. Rev. 1.00 Jan. 29, 2008 Page 480 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 However, at other times (indicated as (b) in figure 14.23) the value set in the TRS bit is put on hold until the next rising edge of the 9th clock cycle or stop condition is detected, rather than taking effect immediately. This results in the actual internal value of the TRS bit remaining 1 (transmit mode) and no acknowledge bit being sent at the 9th clock cycle address receive completion in the case of an address receive operation following a restart condition input with no stop condition intervening. When receiving an address in the slave mode, clear the TRS bit to 0 during the period indicated as (a) in figure 14.23. To cancel the holding of the SCL bit low by the wait function in the slave mode, clear the TRS bit to 0 and then perform a dummy read of the ICDR register. Restart condition (a) SDA SCL TRS 8 9 1 2 3 4 5 6 7 8 (b) A 9 Data transmission Address reception TRS bit setting hold time ICDR dummy read TRS bit set Detection of 9th clock cycle rising edge Detection of 9th clock cycle rising edge Figure 14.23 TRS Bit Setting Timing in Slave Mode 13. Notes on ICDR Reads in Transmit Mode and ICDR Writes in Receive Mode When attempting to read ICDR in the transmit mode (TRS = 1) or write to ICDR in the receive mode (TRS = 0) under certain conditions, the SCL pin may not be held low after the completion of the transmit or receive operation and a clock may not be output to the SCL bus line before the ICDR register access operation can take place properly. When accessing ICDR, always change the setting to the transmit mode before performing a read operation, and always change the setting to the receive mode before performing a write operation. Rev. 1.00 Jan. 29, 2008 Page 481 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 14. Notes on ACKE Bit and TRS Bit in Slave Mode When using the I2C bus interface, if an address is received in the slave mode immediately after 1 is received as an acknowledge bit (ACKB = 1) in the transmit mode (TRS = 1), an interrupt may be generated at the rising edge of the 9th clock cycle if the address does not match. When performing slave mode operations using the IIC bus interface module, make sure to do the following. (a) When a 1 is received as an acknowledge bit for the final transmit data after completing a series of transmit operations, clear the ACKE bit in the ICCR register to 0 to initialize the ACKB bit to 0. (b) In the slave mode, change the setting to the receive mode (TRS = 0) before the start condition is input. To ensure that the switch from the slave transmit mode to the slave receive mode is accomplished properly, end the transmission as described in figure 14.14. 15. Notes on Arbitration Lost in Master Mode The I2C bus interface recognizes the data in transmit/receive frame as an address when arbitration is lost in master mode and a transition to slave receive mode is automatically carried out. When arbitration is lost not in the first frame but in the second frame or subsequent frame, transmit/receive data that is not an address is compared with the value set in the SAR or SARX register as an address. If the receive data matches with the address in the SAR or SARX register, the I2C bus interface erroneously recognizes that the address call has occurred. (See figure 14.24.) In multi-master mode, a bus conflict could happen. When The I2C bus interface is operated in master mode, check the state of the AL bit in the ICSR register every time after one frame of data has been transmitted or received. When arbitration is lost during transmitting the second frame or subsequent frame, take avoidance measures. Rev. 1.00 Jan. 29, 2008 Page 482 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 * Arbitration is lost * The AL flag in ICSR is set to 1 bus interface (Master transmit mode) I2C S SLA R/W A Transmit data match Transmit timing match DATA1 Transmit data does not match Other device (Master transmit mode) S SLA R/W A DATA2 A DATA3 A Data contention I2C bus interface (Slave receive mode) S SLA R/W A SLA R/W A DATA4 A * Receive address is ignored * Automatically transferred to slave receive mode * Receive data is recognized as an address * When the receive data matches to the address set in the SAR or SARX register, the I2C bus interface operates as a slave device. Figure 14.24 Diagram of Erroneous Operation when Arbitration is Lost Though it is prohibited in the normal I2C protocol, the same problem may occur when the MST bit is erroneously set to 1 and a transition to master mode is occurred during data transmission or reception in slave mode. In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order below. (a) Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting the MST bit. (b) Set the MST bit to 1. (c) To confirm that the bus was not entered to the busy state while the MST bit is being set, check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been set. Rev. 1.00 Jan. 29, 2008 Page 483 of 666 REJ09B0427-0100 Section 14 I C Bus Interface 2 16. Notes on Wait Function in Master Mode While the WAIT bit in ICMR is set to 1 and WAIT in master mode, if the interrupt flag of the IRIC bit is cleared from 1 to 0 between the falling edge of the 7th clock and the falling edge of the 8th clock, the clock pulse of the 9th clock may be output continuously due to the failure to insert a wait after the falling edge of the 8th clock. When the wait function is used in master mode, clear the IRIC flag after the IRIC flag is set to 1 on the falling edge of the 9th clock and before the rising edge of the 7th clock (the counter value of BC2 to BC0 should be 2 or greater). If the clearing of the IRIC flag is delayed due to the interrupt or other processes and the value of the RC counter is changed to 1 or 0, confirm that the SCL pins are in the L state after the counter values of BC2 to BC0 are cleared to 0, and then clear the IRIC flag (see figure 14.25). SDA A Transmit/Receive data A Transmit/Receive data SCL 9 1 2 3 4 5 6 7 8 Confirm SCL = L 9 1 2 3 BC2 to BC0 0 7 6 5 4 3 2 1 0 Clear IRIC 7 6 5 Clear IRIC BC2 to BC0 2 IRIC (Example of operation) Clear IRIC flag enabled Clear IRIC flag enabled Clear IRIC flag disabled Figure 14.25 IRIC Flag Clear Timing when the Wait Function is Used 17. Module Stop Mode Setting The IIC operation can be enabled or disabled using the module stop control register. The initial setting is for the IIC operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 21, Power-Down Modes. Rev. 1.00 Jan. 29, 2008 Page 484 of 666 REJ09B0427-0100 Section 15 A/D Converter Section 15 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to twelve analog input channels to be selected. The Block diagram of the A/D converter is shown in figure 15.1. 15.1 * * * * Features * * * * * 10-bit resolution Twelve input channels Conversion time: 13.3 s per channel (at 20-MHz operation) Two operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels Four data registers Conversion results are held in a 16-bit data register for each channel Sample and hold function Three methods conversion start Software 16-bit timer pulse unit (TPU) conversion start trigger External trigger signal Interrupt request An A/D conversion end interrupt request (ADI) can be generated Module stop mode can be set Rev. 1.00 Jan. 29, 2008 Page 485 of 666 REJ09B0427-0100 Section 15 A/D Converter Module data bus Bus interface Internal data bus AVCC Vref AVSS 10-bit D/A Successive approximations register A D D R A A D D R B A D D R C A D D R D A D C S R A D C R AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ADTRG + /2 /4 Comparator Multiplexer Control circuit /8 /16 Sample-andhold circuit ADI interrupt Conversion start trigger from TPU [Legend] ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D Figure 15.1 Block Diagram of A/D Converter Rev. 1.00 Jan. 29, 2008 Page 486 of 666 REJ09B0427-0100 Section 15 A/D Converter 15.2 Input/Output Pins Table 15.1 summarizes the input pins used by the A/D converter. The 12 analog input pins are divided into four channel sets and three groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1, and analog input pins 8 to 11 (AN8 to AN11) comprising group 2. The AVcc and AVss pins are the power supply pins for the analog block in the A/D converter. Table 15.1 Pin Configuration Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 A/D external trigger input pin Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input External trigger input pin for starting A/D conversion Group 2 analog input pins Group 1 analog input pins Function Analog block power supply and reference voltage Analog block ground and reference voltage A/D conversion reference voltage Group 0 analog input pins Rev. 1.00 Jan. 29, 2008 Page 487 of 666 REJ09B0427-0100 Section 15 A/D Converter 15.3 Register Description The A/D converter has the following registers. The MSTPA1 bit in the module stop control * * * * * * A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) A/D Data Registers A to D (ADDRA to ADDRD) 15.3.1 There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 15.2. The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. When reading the ADDR, read the upper byte before the lower byte, or read in word unit. When only the lower byte is read, the contents are not guaranteed. Table 15.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel CH3 = 0 Group 0 (CH2 = 0) AN0 AN1 AN2 AN3 Group 1 (CH2 = 1) AN4 AN5 AN6 AN7 Group 2 (CH2 = 0) AN8 AN9 AN10 AN11 CH3 = 1 -- (CH2 = 1) Setting prohibited Setting prohibited Setting prohibited Setting prohibited A/D Data Register to Be Stored the Results of A/D Conversion ADDRA ADDRB ADDRC ADDRD Rev. 1.00 Jan. 29, 2008 Page 488 of 666 REJ09B0427-0100 Section 15 A/D Converter 15.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit 7 Bit Name ADF Initial Value 0 R/W R/(W) Description A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends When A/D conversion ends on all specified channels [Clearing conditions] * * When 0 is written after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read 6 ADIE 0 R/W A/D Interrupt Enable A/D conversion end interrupt (ADI) request enabled when 1 is set Rev. 1.00 Jan. 29, 2008 Page 489 of 666 REJ09B0427-0100 Section 15 A/D Converter Bit 5 Bit Name ADST Initial Value 0 R/W R/W Description A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters the wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bits is cleared to 0 automatically when conversion on the specified channel is complete. In scan mode, conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or a transition to software standby mode, hardware standby mode or module stop mode. 4 SCAN 0 R/W Scan Mode Selects single mode or scan mode as the A/D conversion operating mode. 0: Single mode 1: Scan mode 3 2 1 0 CH3 CH2 CH1 CH0 0 0 0 0 R/W R/W R/W R/W Channel Select 0 to 3 Select analog input channels. When SCAN = 0 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1000: AN8 1001: AN9 1010: AN10 1011: AN11 1100: Setting prohibited 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited When SCAN = 1 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN4 0101: AN4 and AN5 0110: AN4 to AN6 0111: AN4 to AN7 1000: AN8 1001: AN8 and AN9 1010: AN8 to AN10 1011: AN8 to AN11 1100: Setting prohibited 1101: Setting prohibited 1110: Setting prohibited 1111: Setting prohibited Rev. 1.00 Jan. 29, 2008 Page 490 of 666 REJ09B0427-0100 Section 15 A/D Converter 15.3.3 A/D Control Register (ADCR) The ADCR enables A/D conversion started by an external trigger signal. Bit 7 6 Bit Name TRGS1 TRGS0 Initial Value 0 0 R/W R/W R/W Description Timer Trigger Select 0 and 1 Enables the start of A/D conversion by a trigger signal. Only set bits TRGS0 and TRGS1 while conversion is stopped (ADST = 0). 00: A/D conversion start by software is enabled 01: A/D conversion start by TPU conversion start trigger is enabled 10: Setting prohibited 11: A/D conversion start by external trigger pin (ADTRG) is enabled 5, 4 3 2 -- CKS1 CKS0 All 1 0 0 -- R/W R/W Reserved These bits are always read as 1. Clock Select 0 and 1 These bits specify the A/D conversion time. The conversion time should be changed only when ADST = 0. Specify a setting that gives a value within the range shown in table 20.7. 00: Conversion time = 530 states (max.) 01: Conversion time = 266 states (max.) 10: Conversion time = 134 states (max.) 11: Conversion time = 68 states (max.) 1, 0 -- All 1 -- Reserved These bits are always read as 1. Rev. 1.00 Jan. 29, 2008 Page 491 of 666 REJ09B0427-0100 Section 15 A/D Converter 15.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 15.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. The operations are as follows. 1. A/D conversion is started when the ADST bit is set to 1, according to software or external trigger input. 2. When A/D conversion is completed, the result is transferred to the corresponding A/D data register to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D converion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the wait state. 15.4.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the specified channels (four channels maximum). The operations are as follows. 1. When the ADST bit is set to 1 by software, TPU or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH3 and CH2 = 00, AN4 when CH3 and CH2 = 01, or AN8 when CH3 and CH2 = 10). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion of the first channel in the group starts again. 4. Steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the wait state. Rev. 1.00 Jan. 29, 2008 Page 492 of 666 REJ09B0427-0100 Section 15 A/D Converter 15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 15.2 shows the A/D conversion timing. Table 15.3 shows the A/D conversion time. As indicated in figure 15.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15.3. In scan mode, the values given in table 15.3 apply to the first conversion time. The values given in table 15.4 apply to the second and subsequent conversions. In both cases, set bits CKS1 and CKS0 in ADCR to give an A/D conversion time within the range shown in table 23.10. (1) Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1): ADCSR write cycle (2) ADCSR address A/D conversion start delay tD: tSPL: Input sampling time tCONV: A/D conversion time Figure 15.2 A/D Conversion Timing Rev. 1.00 Jan. 29, 2008 Page 493 of 666 REJ09B0427-0100 Section 15 A/D Converter Table 15.3 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 Item CKS0 = 1 CKS1 = 1 CKS0 = 0 CKS0 = 1 Min. Typ. Max. 4 -- 67 -- 15 -- 5 -- 68 Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 18 -- -- 33 10 -- -- 63 17 -- 266 6 -- -- 31 9 -- 134 A/D conversion tD start delay Input sampling time tSPL 127 -- 530 A/D conversion tCONV time 515 -- 259 -- 131 -- Note: All values represent the number of states. Table 15.4 A/D Conversion Time (Scan Mode) CKS1 0 CKS0 0 1 1 0 1 Conversion Time (State) 512 (Fixed) 256 (Fixed) 128 (Fixed) 64 (Fixed) Rev. 1.00 Jan. 29, 2008 Page 494 of 666 REJ09B0427-0100 Section 15 A/D Converter 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 15.3 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 15.3 External Trigger Input Timing 15.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the bit ADF in ADCSR is set to 1 after A/D conversion is completed. The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion without imposing a load on software. Table 15.5 A/D Converter Interrupt Source Name ADI Interrupt Source A/D conversion completed Interrupt Source Flag ADF DTC Activation Possible Rev. 1.00 Jan. 29, 2008 Page 495 of 666 REJ09B0427-0100 Section 15 A/D Converter 15.6 A/D Conversion Precision Definitions This LSI's A/D conversion precision definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 15.4). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'00) to B'0000000001 (H'01) (see figure 15.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3E) to B'1111111111 (H'3F) (see figure 15.5). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between zero voltage and fullscale voltage. Does not include offset error, full-scale error, or quantization error (see figure 15.5). * Absolute precision The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error. Rev. 1.00 Jan. 29, 2008 Page 496 of 666 REJ09B0427-0100 Section 15 A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 15.4 A/D Conversion Precision Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage Offset error Figure 15.5 A/D Conversion Precision Definitions Rev. 1.00 Jan. 29, 2008 Page 497 of 666 REJ09B0427-0100 Section 15 A/D Converter 15.7 15.7.1 Usage Notes Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 21, Power-Down Modes. 15.7.2 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it may not be possible to guarantee A/D conversion precision. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 15.6). When converting a high-speed analog signal, a low-impedance buffer should be inserted. 15.7.3 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e, acting as antennas). Rev. 1.00 Jan. 29, 2008 Page 498 of 666 REJ09B0427-0100 Section 15 A/D Converter This LSI Sensor output impedance to 5 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF A/D converter equivalent circuit 10 k 20 pF Figure 15.6 Example of Analog Input Circuit 15.7.4 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss VAN AVcc. * Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss as the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open. * Range of Vref pin setting Vref pin reference voltage setting should be in the range Vref AVCC. 15.7.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN11), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable digital ground (Vss) on the board. Rev. 1.00 Jan. 29, 2008 Page 499 of 666 REJ09B0427-0100 Section 15 A/D Converter 15.7.6 Notes on Noise Countermeasures A protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN0 to AN11), between AVcc and AVss, as shown in figure 15.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN11 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN11) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding circuit constants. AVCC Rin*2 *1 0.1 F 100 AN0 to AN11 AVSS Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 15.7 Example of Analog Input Protection Circuit Rev. 1.00 Jan. 29, 2008 Page 500 of 666 REJ09B0427-0100 Section 15 A/D Converter Table 15.6 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min -- -- Max 20 5 Unit pF k 10 k AN0 to AN11 To A/D converter 20 pF Note: Values are reference values. Figure 15.8 Analog Input Pin Equivalent Circuit Rev. 1.00 Jan. 29, 2008 Page 501 of 666 REJ09B0427-0100 Section 15 A/D Converter Rev. 1.00 Jan. 29, 2008 Page 502 of 666 REJ09B0427-0100 Section 16 D/A Converter Section 16 D/A Converter 16.1 * * * * * Features 8-bit resolution Two output channels Conversion time: Max. 10 s (when load capacitance is 20 pF) Output voltage: 0 V to Vref D/A output retaining function in software standby mode Module data bus Internal data bus Vref AVCC DA1 DA0 AVSS 8-bit D/A D A D R 0 D A D R 1 D A C R Control circuit Legend: DACR : D/A control register DADR0 : D/A data register 0 DADR1 : D/A data register 1 Figure 16.1 Block Diagram of D/A Converter Rev. 1.00 Jan. 29, 2008 Page 503 of 666 REJ09B0427-0100 Bus interface Section 16 D/A Converter 16.2 Input/Output Pins Table 16.1 summarizes the input/output pins used by the D/A converter. Table 16.1 Pin Configuration Pin Name Analog power supply pin Analog ground pin Analog output pin 0 Analog output pin 1 Symbol AVCC AVSS DA0 DA1 I/O Input Input Output Output Input Function Analog block power supply Analog block ground and reference voltage Channel 0 analog output Channel 1 analog output Analog block reference voltage Reference power supply pin Vref 16.3 Register Descriptions The D/A converter has the following registers. * D/A data register 0 (DADR0) * D/A data register 1 (DADR1) * D/A control register (DACR) 16.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) DADR0 and DADR1 are 8-bit readable/writable registers that store data for D/A conversion. When analog output is permitted, DADR contents are converted and output to analog output pins. DADR0 and DADR1 are initialized to H'00. Rev. 1.00 Jan. 29, 2008 Page 504 of 666 REJ09B0427-0100 Section 16 D/A Converter 16.3.2 D/A Control Register (DACR) DACR controls D/A converter operation. Bit 7 Bit Name Initial Value DAOE1 0 R/W R/W Description D/A Output Enable 1 Controls D/A conversion and analog output. 0: Analog output DA1 is disabled 1: D/A conversion for channel 1 and analog output DA1 are enabled 6 DAOE0 0 R/W D/A Output Enable 0 Controls D/A conversion and analog output. 0: Analog output DA0 is disabled 1: D/A conversion for channel 0 and analog output DA0 are enabled 5 DAE 0 R/W D/A Enable Controls D/A conversion in conjunction with the DAOE0 and DAOE1 bits. When the DAE bit is cleared to 0, D/A conversion for channels 0 and 1 is controlled individually. When the DAE bit is set to 1, D/A conversion for channels 0 and 1 are controlled as one. Conversion result output is controlled by the DAOE0 and DAOE1 bits. For details, see table 16.2 below. 4 to 0 -- All 1 R Reserved These bits are always read as 1 and cannot be modified. Rev. 1.00 Jan. 29, 2008 Page 505 of 666 REJ09B0427-0100 Section 16 D/A Converter Table 16.2 D/A Channel Enable Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE -- 0 1 1 0 0 1 1 -- Description Disables D/A conversion Enables D/A conversion for channel 0 Disables D/A conversion for channel 1 Enables D/A conversion for channels 0 and 1 Disables D/A conversion for channel 0 Enables D/A conversion for channel 1 Enables D/A conversion for channels 0 and 1 Enables D/A conversion for channels 0 and 1 16.4 Operation The D/A converter incorporates two channels of the D/A circuits and can be converted individually. When the DAOE bit in DACR is set to 1, D/A conversion is enabled and conversion results are output. An example of D/A conversion of channel 0 is shown below. The operation timing is shown in figure 16.2. 1. Write conversion data to DADR0. 2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. After the interval of tDCONV, conversion results are output from the analog output pin DA0. The conversion results are output continuously until DADR0 is modified or the DAOE0 bit is cleared to 0. The output value is calculated by the following formula: DADR contents/256 x Vref 3. Conversion starts immediately after DADR0 is modified. After the interval of tDCONV, conversion results are output. 4. When the DAOE0 bit is cleared to 0, analog output is disabled. Rev. 1.00 Jan. 29, 2008 Page 506 of 666 REJ09B0427-0100 Section 16 D/A Converter DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle Address DADR0 Conversion data (1) Conversion data (2) DAOE0 Conversion result (2) tDCONV DA0 High impedance state tDCONV Conversion result (1) Legend: tDCONV: D/A conversion time Figure 16.2 D/A Converter Operation Example Rev. 1.00 Jan. 29, 2008 Page 507 of 666 REJ09B0427-0100 Section 16 D/A Converter 16.5 Usage Note When this LSI enters software standby mode with D/A conversion enabled, the D/A output is retained, and the analog power supply current is equal to as during D/A conversion. If the analog power supply current needs to be reduced in software standby mode, clear the DAOE1, DAOE0, and DAE bits all to 0 to disable D/A output. 16.5.1 Module Stop Mode Setting D/A converter operation can be enabled or disabled using the module stop control register. The initial setting is for D/A converter operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 21, Power-Down Modes. Rev. 1.00 Jan. 29, 2008 Page 508 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) Section 17 Motor Control PWM Timer (PWM) This LSI has on-chip motor control PWM (pulse width modulator) with a maximum capability of 16 pulse outputs in total. 17.1 Features * Maximum of 16 pulse outputs Two 10-bit PWM channels, each with eight outputs. 10-bit counter (PWCNT) and cycle register (PWCYR). Duty and output polarity can be set for each output. * Automatic data transfer in every cycle Each of four duty registers (PWDTR) is provided with buffer registers (PWBFR), with data transferred automatically every cycle. Channel 1 is provided with four duty registers and four buffer registers. Channel 2 is provided with eight duty registers and four buffer registers. * Duty settings selectable A duty cycle of 0% to 100% can be selected by means of a duty register setting. * Operating clock selectable There is a choice of five operating clocks (, /2, /4, /8, /16). * High-speed access via internal 16-bit bus * Two interrupt sources An interrupt can be requested independently for each channel by a cycle register compare match. * Automatic transfer of register data Block transfer and one-word data transfer are available by activating the data transfer controller (DTC). * Module stop mode can be set Rev. 1.00 Jan. 29, 2008 Page 509 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) Figure 17.1 shows a block diagram of PWM_1. , /2, /4, /8, /16 Interrupt request PWCR_1 Compare match PWCNT_1 PWOCR_1 Port control PWCYR_1 12 9 0 PWPR_1 Bus interface Internal data bus 12 9 0 PWBFR_1A PWDTR_1A P/N P/N P/N P/N P/N P/N P/N P/N PWM1A PWM1B PWM1C PWM1D PWM1E PWM1F PWM1G PWM1H PWBFR_1C PWDTR_1C PWBFR_1E PWDTR_1E PWBFR_1G PWDTR_1G [Legend] PWCR_1: PWOCR_1: PWPR_1: PWCNT_1: PWCYR_1: PWDTR_1A, _1C, _1E, _1G: PWBFR_1A, _1C, _1E, _1G: PWM control register PWM output control register PWM polarity register PWM counter PWM cycle register PWM duty registers_1A, _1C, _1E, _1G PWM buffer registers_1A, _1C, _1E, _1G Figure 17.1 Block Diagram of PWM_1 Rev. 1.00 Jan. 29, 2008 Page 510 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) Figure 17.2 shows a block diagram of PWM_2. , /2, /4, /8, /16 Interrupt request PWCR_2 PWCNT_2 PWOCR_2 Port control Compare match PWCYR_2 9 0 PWPR_2 12 9 0 PWBFR_2A PWDTR_2A P/N PWM2A Internal data bus Bus interface PWBFR_2B PWDTR_2B P/N PWM2B PWBFR_2C PWDTR_2C P/N PWM2C PWBFR_2D PWDTR_2D PWDTR_2E PWDTR_2F PWDTR_2G PWDTR_2H P/N P/N P/N P/N P/N PWM2D PWM2E PWM2F PWM2G PWM2H [Legend] PWCR_2 PWOCR_2 PWPR_2 PWCNT_2 PWCYR_2 PWDTR_2A, _2B, _2C, _2D, _2E, _2F, _2G, _2H PWBFR_2A, _2B, _2C, _2D PWM control register_2 PWM output control register_2 PWM polarity register_2 PWM counter_2 PWM cycle register_2 PWM duty registers_2A, _2B, _2C, _2D, _2E, _2F, _2G, _2H PWM buffer registers_2A, _2B, _2C, _2D Figure 17.2 Block Diagram of PWM_2 Rev. 1.00 Jan. 29, 2008 Page 511 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) 17.2 Input/Output Pins Table 17.1 shows the PWM pin configuration. Table 17.1 Pin Configuration Channel 1 Name PWM output pin 1A PWM output pin 1B PWM output pin 1C PWM output pin 1D PWM output pin 1E PWM output pin 1F PWM output pin 1G PWM output pin 1H 2 PWM output pin 2A PWM output pin 2B PWM output pin 2C PWM output pin 2D PWM output pin 2E PWM output pin 2F PWM output pin 2G PWM output pin 2H Abbrev. PWM1A PWM1B PWM1C PWM1D PWM1E PWM1F PWM1G PWM1H PWM2A PWM2B PWM2C PWM2D PWM2E PWM2F PWM2G PWM2H I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Function Channel 1A PWM output Channel 1B PWM output Channel 1C PWM output Channel 1D PWM output Channel 1E PWM output Channel 1F PWM output Channel 1G PWM output Channel 1H PWM output Channel 2A PWM output Channel 2B PWM output Channel 2C PWM output Channel 2D PWM output Channel 2E PWM output Channel 2F PWM output Channel 2G PWM output Channel 2H PWM output Rev. 1.00 Jan. 29, 2008 Page 512 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) 17.3 Register Descriptions The PWM has the following registers for each channel. * * * * * * * PWM control register (PWCR) PWM output control register (PWOCR) PWM polarity register (PWPR) PWM counter (PWCNT) PWM cycle register (PWCYR) PWM duty register (PWDTR) PWM buffer register (PWBFR) Rev. 1.00 Jan. 29, 2008 Page 513 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) 17.3.1 PWM Control Register (PWCR) PWCR performs interrupt control, starting/stopping of the counter, and counter clock selection. It also contains a flag that indicates a compare match with PWCYR. Bit 7, 6 Bit Name Initial Value All 1 R/W Description Reserved These bits are always read as 1 and cannot be modified. 5 IE 0 R/W Interrupt Enable Enables or disables an interrupt request in the event of a compare match with PWCYR of the corresponding channel. 0: Interrupt disabled 1: Interrupt enabled 4 CMF 0 R/(W)* Compare Match Flag Indicates the occurrence of a compare match with PWCYR of the corresponding channel. [Setting condition] When PWCNT = PWCYR [Clearing condition] * * 3 CST 0 R/W When 0 is written to CMF after reading CMF = 1 When the DTC is activated by a compare match interrupt, and the DISEL bit in MRB of the DTC is 0 Counter Start Selects starting or stopping of PWCNT of the corresponding channel. 0: PWCNT is stopped 1: PWCNT is started Rev. 1.00 Jan. 29, 2008 Page 514 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) Bit 2 1 0 Bit Name CKS2 CKS1 CKS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Clock Select These bits select the operating clock for PWCNT of the corresponding channel. 000: Counts on /1 001: Counts on /2 010: Counts on /4 011: Counts on /8 1xx: Counts on /16 [Legend] x: Don't care Note: * Only 0 can be written, to clear the flag. 17.3.2 PWM Output Control Register (PWOCR) PWOCR enables or disables PWM output. Bit 7 6 5 4 3 2 1 0 (n = 1, 2) Bit Name OEnH OEnG OEnF OEnE OEnD OEnC OEnB OEnA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Enable Each of these bits enables or disables the corresponding PWM output. 0: PWM output disabled 1: PWM output enabled Rev. 1.00 Jan. 29, 2008 Page 515 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) 17.3.3 PWM Polarity Register (PWPR) PWPR selects the PWM output polarity. Bit 7 6 5 4 3 2 1 0 (n = 1, 2) Bit Name OPSnH OPSnG OPSnF OPSnE OPSnD OPSnC OPSnB OPSnA Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Polarity Select Each of these bits selects the PWM output polarity. 0: PWM direct output 1: PWM inverse output 17.3.4 PWM Counter (PWCNT) PWCNT is a 10-bit up-counter incremented by the input clock. The input clock is selected by clock select bits CKS2 to CKS0 in PWCR. PWCNT can not be directly accessed by the CPU. PWCNT is initialized to H'FC00, when CST bit in PWCR is 0. Rev. 1.00 Jan. 29, 2008 Page 516 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) 17.3.5 PWM Cycle Register (PWCYR) PWCYR is a 16-bit readable/writable register that sets the PWM conversion cycle. When a PWCYR compare match occurs, PWCNT is cleared and data is transferred from the buffer register (PWBFR) to the duty register (PWDTR). PWCYR should be written to only while PWCNT is stopped. A value of H'FC00 must not be set. PWCYR is initialized to H'FFFF. Compare match PWCNT (lower 10 bits) PWCYR (lower 10 bits) 0 1 Compare match N-2 N-1 0 1 N Figure 17.3 Cycle Register Compare Match Rev. 1.00 Jan. 29, 2008 Page 517 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) 17.3.6 PWM Duty Registers (PWDTR) * PWM_1 PWDTR_1 has four PWDTR registers (PWDTR_A, PWDTR_C, PWDTR_E, and PWDTR_G). The PWDTR_1A is used for outputs PWM1A and PWM1B, PWDTR_1C for outputs PWM1C and PWM1D, PWDTR_1E for outputs PWM1E and PWM1F, and PWDTR_1G for outputs PWM1G and PWM1H. PWDTR_1 cannot be directly accessed by the CPU. When a PWCYR_1 compare match occurs, data is transferred from the buffer register (PWBFR) to the duty register (PWDTR). PWDTR_1 is initialized to H'EC00 when the CST bit is 0. Initial Value All 1 0 Bit 15 to 13 12 Bit Name OTS R/W Description Reserved Output Terminal Select Bit 12 selects the pin used for PWM output according to the value in bit 12 in the buffer registers that is transferred by a PWCYR_1 compare match. Unselected pins output a low level (or a high level when the corresponding bit in PWPR_1 is set to 1). For details, see table 17.2. 11, 10 9 8 7 6 5 4 3 2 1 0 DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 1 0 0 0 0 0 0 0 0 0 0 Reserved Duty These bits specify the PWM output duty. A high level (or a low level when the corresponding bit in PWPR is set to 1) is output from the time PWCNT_1 is cleared by a PWCYR_1 compare match until a PWDTR_1 compare match occurs. When all of the bits are 0, there is no high-level (or low-level when the corresponding bit in PWPR is set to 1) output period. Rev. 1.00 Jan. 29, 2008 Page 518 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) Table 17.2 Output Selection by OTS Bit Bit 12 Register PWDTR_1A OTS 0 1 PWDTR_1C 0 1 PWDTR_1E 0 1 PWDTR_1G 0 1 Description PWM1A output selected PWM1B output selected PWM1C output selected PWM1D output selected PWM1E output selected PWM1F output selected PWM1G output selected PWM1H output selected Compare match PWCNT_1 (lower 10 bits) PWCYR_1 (lower 10 bits) PWDTR_1 (lower 10 bits) PWM output on selected pin PWM output on unselected pin 0 1 M-2 M-1 M N-1 0 N M Figure 17.4 Duty Register Compare Match (OPS = 0 in PWPR_1) Rev. 1.00 Jan. 29, 2008 Page 519 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) PWCNT_1 (lower 10 bits) PWCYR_1 (lower 10 bits) PWDTR_1 (lower 10 bits) PWM output (M = 0) PWM output (0 < M < N) PWM output (N M) 0 1 N-2 N-1 0 N M Figure 17.5 Differences in PWM Output According to Duty Register Set Value (OPS = 0 in PWPR_1) * PWM_2 PWDTR_2 has eight registers (PWDTR2A to 2H). The PWDTR_2A is used for outputs PWM2A, PWDTR_2B for outputs PWM2B, PWDTR_2C for outputs PWM2C, PWDTR_2D for outputs PWM2D, PWDTR_2E for outputs PWM2E, PWDTR_2F for outputs PWM2F, PWDTR_2G for outputs PWM2G, PWDTR_2H for outputs PWM2H. PWDTR_2 cannot be directly read or written. When a PWCYR_2 compare match occurs, data is transferred from the buffer register_2 (PWBFR_2) to the PWDTR_2. PWDTR_2 is initialized to H'EC00 when the Counter Start bit (CST) in PWCR_2 is 0. Rev. 1.00 Jan. 29, 2008 Page 520 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) Bit 15 to 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Initial Value All 1 0 1 1 0 0 0 0 0 0 0 0 0 0 R/W Description Reserved Reserved Reserved Duty Bits 9 to 0 set PWM output duty according to the values in bits 9 to 0 in the buffer register that is transferred by a PWCYR_2 compare match. A high level (or a low level when the corresponding bit in PWPR is set to 1) is output from the time PWCNT_2 is cleared by a PWCYR_2 compare match until a PWDTR compare match occurs. When all of the bits are 0, there is no high-level (or low-level when the corresponding bit in PWPR is set to 1) output period. Compare match PWCNT_2 (lower 10 bits) PWCYR_2 (lower 10 bits) PWDTR_2 (lower 10 bits) PWM output 0 1 M-2 M-1 M N-1 0 N M Figure 17.6 Duty Register Compare Match (OPS = 0 in PWPR_2) Rev. 1.00 Jan. 29, 2008 Page 521 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) PWCNT_2 (lower 10 bits) PWCYR_2 (lower 10 bits) PWDTR_2 (lower 10 bits) PWM output (M = 0) PWM output (0 < M < N) PWM output (N M) 0 1 N-2 N-1 0 N M Figure 17.7 Differences in PWM Output According to Duty Register Set Value (OPS = 0 in PWPR_2) Rev. 1.00 Jan. 29, 2008 Page 522 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) 17.3.7 PWM Buffer Register (PWBFR) * PWM_1 There are four PWBFR_1 registers (PWBFR_A, PWBFR_C, PWBFR_E, and PWBFR_G). When a PWCYR_1 compare match occurs, data is transferred from the buffer register (PWBFR) to the duty register (PWDTR). Bit 15 to 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name OTS DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Initial Value All 1 0 1 1 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved These bits are always read as 1 and cannot be modified. Output Terminal Select Holds the data to be sent to bit 12 in PWDTR1. Reserved These bits are always read as 1 and cannot be modified. Duty These bits hold the data to be sent to bits 9 to 0 in PWDTR_1. * PWM_2 There are four 16 bit read/write PWBFR_2 registers (PWBFR2A to PWBFR2D). When a PWCYR_2 compare match occurs, data is transferred from PWBFR_2A to PWDTR_2A or PWDTR_2E, from PWBFR_2B to PWDTR_2B or PWDTR_2F, from PWBFR_2C to PWDTR_2C or PWDTR_2G, and from PWBFR_2D to PWDTR_2D or PWDTR_2H. The transfer determination is determined by the value of the TDS bit. Rev. 1.00 Jan. 29, 2008 Page 523 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) Bit 15 to 13 12 Bit Name TDS Initial Value All 1 0 R/W R/W Description Reserved These bits are always read as 1 and cannot be modified. Transfer Destination Select (TDS) Bit 12 selects the PWDTR2 register to which data is to be transferred. 11 10 9 8 7 6 5 4 3 2 1 0 DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 1 1 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reserved These bits are always read as 1 and cannot be modified. Duty The data is transferred to bits 9 to 0 in PWDTR_2. Table 17.3 Output Selection by TDS Bit Bit 12 Register PWBFR_2A/ TDS 0 1 PWBFR_2B 0 1 PWBFR_2C 0 1 PWBFR_2D 0 1 Description PWDTR_2A selected PWDTR_2E selected PWDTR_2B selected PWDTR_2F selected PWDTR_2C selected PWDTR_2G selected PWDTR_2D selected PWDTR_2H selected Rev. 1.00 Jan. 29, 2008 Page 524 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) 17.4 17.4.1 Bus Master Interface 16-Bit Data Registers PWCYR and PWBFR are 16-bit registers. These registers are linked to the bus master by a 16-bit data bus, and can be read or written in 16-bit units. They cannot be read or written by 8-bit access; 16-bit access must always be used. Internal data bus H Bus master L Bus interface Module data bus PWCYR Figure 17.8 16-Bit Register Access Operation (Bus Master PWCYR (16 Bits)) 17.4.2 8-Bit Data Registers PWCR, PWOCR, and PWPR are 8-bit registers that can be read and written to in 8-bit units. These registers are linked to the bus master by a 16-bit data bus, and can be read or written by 16bit access; in this case, the lower eight bits are read as an undefined value. Internal data bus H Bus master L Bus interface Module data bus PWCR Figure 17.9 8-Bit Register Access Operation (Bus Master PWCR (Upper Eight Bits)) Rev. 1.00 Jan. 29, 2008 Page 525 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) 17.5 17.5.1 Operation PWM_1 Operation PWM waveforms are output from pins PWM1A to PWM1H and PWM2A to PWM2H as shown in figure 17.10. Initial Settings: Set the PWM output polarity in PWPR; set the OEn bit in PWOCR to 1 to enable PWM output from the corresponding pin; select the clock to be input to PWCNT with the CKS2 to CKS0 bits in PWCR; set the PWM conversion cycle in PWCYR; and set the first frame of data in PWBFRA, PWBFRC, PWBFRE, and PWBFRG. Activation: Setting the CST bit in PWCR to 1 starts counting by PWCNT. When a compare match between PWCNT and PWCYR occurs, data is transferred from the buffer register to the duty register and the CMF bit in PWCR is set to 1. If the IE bit in PWCR has been set to 1 at this time, an interrupt can be requested or the DTC can be activated. Waveform Output: The PWM outputs selected by the OTS bits in PWDTRA, PWDTRC, PWDTRE, and PWDTRG go high when a compare match occurs between PWCNT and PWCYR. The PWM outputs not selected by the OTS bit are low. When a compare match occurs between PWCNT and PWDTRA, PWDTRC, PWDTRE, or PWDTRG, the corresponding PWM output goes low. If the corresponding bit in PWPR is set to 1, the output is inverted. PWCYR_1 PWBFR_1A PWDTR_1A OTS (PWDTRA) = 0 OTS (PWDTRA) = 1 OTS (PWDTRA) = 0 OTS (PWDTRA) = 1 PWM1A PWM1B Figure 17.10 PWM_1 Operation Next Frame: When a compare match occurs between PWCNT and PWCYR, data is transferred from the buffer register to the duty register. PWCNT is reset and starts counting up from H'000. The CMF bit in PWCR is set, and if the IE bit in PWCR1 or PWCR2 has been set, an interrupt can be requested or the DTC can be activated. Rev. 1.00 Jan. 29, 2008 Page 526 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) Stopping: When the CST bit in PWCR is cleared to 0, PWCNT is reset and stops. All PWM outputs go low (or high if the corresponding bit in PWPR is set to 1). 17.5.2 PWM_2 Operation PWM waveforms are output from pins PWM2A to PWM2H as shown in Figure 17.11. Initial Settings: Set the PWM output polarity in PWPR2; enable the pins for PWM output with PWOCR2; select the clock to be input to PWCNT2 with bits CKS2 to CKS0 in PWCR2; set the PWM conversion cycle in PWCYR2; and set the first frame of data in PWBFR2A, PWBFR2B, PWBFR2C, and PWBFR2D. Activation: When the CST bit in PWCR2 is set to 1, a compare match between PWCNT2 and PWCYR2 is generated. Data is transferred from PWBFR2A to PWDTR2A or PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or PWDTR2G, and from PWBFR2D to PWDTR2D or PWDTR2H, according to the value of the TDS bit. PWCNT2 starts counting up. At the same time the CMF bit in PWCR2 is set, so that, if the IE bit in PWCR2 has been set, an interrupt can be requested or the DTC can be activated. Waveform Output: The PWM outputs go high when a compare match occurs between PWCNT2 and PWCYR2. When a compare match occurs between PWCNT2 and PWDTR2A to PWDTR2H, the corresponding PWM output goes low. If the corresponding bit in PWPR2 is set to 1, the output is inverted. PWCYR_2 PWBFR_2A PWDTR_2A PWDTR_2E TDS (PWBFR2A) = 0 TDS (PWBFR2A) = 1 TDS (PWBFR2A) = 0 PWM2A PWM2B Figure 17.11 PWM_2 Operation Next Frame: When a compare match occurs between PWCNT2 and PWCYR2, data is transferred from PWBFR2A to PWDTR2A or PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or PWDTR2G, and from PWBFR2D to PWDTR2D or PWDTR2H, according to the value of the TDS bit. PWCNT2 is reset and starts counting up from Rev. 1.00 Jan. 29, 2008 Page 527 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) H'000. The CMF bit in PWCR2 is set, and if the IE bit in PWCR2 has been set, an interrupt can be requested or the DTC can be activated. Stopping: When the CST bit in PWCR2 is cleared to 0, PWCNT2 is reset and stops. PWDTR2A to PWDTR2H are reset. All PWM outputs go low (or high if the corresponding bit in PWPR2 is set to 1). Rev. 1.00 Jan. 29, 2008 Page 528 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) 17.6 17.6.1 Usage Note Conflict between Buffer Register Write and Compare Match If a PWBFR write is performed in the state immediately after a cycle register compare match, the buffer register and duty register are both modified. PWM output changed by the cycle register compare match is not changed by modification of the duty register due to conflict. This may result in unanticipated duty output. Buffer register modification must be completed before automatic transfer by the DTC, exception handling due to a compare match interrupt, or the occurrence of a cycle register compare match on detection of the rise of CMF (compare match flag) in PWCR. T1 Address Write signal PWCNT (lower 10 bits) PWBFR PWDTR PWM output CMF N N Buffer register address Tw Tw T2 Compare match 0 M M Figure 17.12 Conflict between Buffer Register Write and Compare Match Rev. 1.00 Jan. 29, 2008 Page 529 of 666 REJ09B0427-0100 Section 17 Motor Control PWM Timer (PWM) Rev. 1.00 Jan. 29, 2008 Page 530 of 666 REJ09B0427-0100 Section 18 RAM Section 18 RAM This LSI has an 16-kbyte on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR). Rev. 1.00 Jan. 29, 2008 Page 531 of 666 REJ09B0427-0100 Section 18 RAM Rev. 1.00 Jan. 29, 2008 Page 532 of 666 REJ09B0427-0100 Section 19 ROM Section 19 ROM The features of the flash memory are summarized below. The block diagram of the flash memory is shown in figure 19.1. 19.1 Features * Size: 384 kbytes * Programming/erase methods The flash memory is programmed in 128-byte units at a time. Erase is performed in singleblock units. The flash memory is configured as follows: 64 kbytes x 5 blocks, 32 kbytes x 1 block, and 4 kbytes x 8 blocks. To erase the entire flash memory, each block must be erased in turn. * Reprogramming capability The flash memory can be reprogrammed for 100 times. * Two on-board programming modes Boot mode User program mode On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program the entire flash memory. In normal user program mode, individual blocks can be erased or programmed. * Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. * Automatic bit rate adjustment For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase operations. Rev. 1.00 Jan. 29, 2008 Page 533 of 666 REJ09B0427-0100 Section 19 ROM * Emulation function for flash memory in RAM The real-time emulation for programming of flash memory is possible by overlapping the flash memory to a part of RAM. Internal address bus Internal data bus (16 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER FLPWCR Bus interface/controller Operating mode FWE pin Mode pin Flash memory [Legend] FLMCR1: FLMCR2: EBR1: EBR2: RAMER: FLPWCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Figure 19.1 Block Diagram of Flash Memory 19.2 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 19.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program, and programmer modes are provided as modes to program and erase the flash memory. The differences between boot mode and user program mode are shown in table 19.1. Rev. 1.00 Jan. 29, 2008 Page 534 of 666 REJ09B0427-0100 Section 19 ROM Figure 19.3 shows the operation flow for boot mode and figure 19.4 shows that for user program mode. MD1 = 1, MD2 = 1, FWE = 0*1 Reset state User mode with on-chip ROM enabled RES = 0 MD1 = 1, MD2 = 1, FWE = 1 RES = 0 RES = 0 MD1 = 0 MD2 = 1, FWE = 1 RES = 0 *2 FWE = 1 FWE = 0 Programmer mode User program mode *1 Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. MD0 = 0, MD1 = 0, MD2 = 0, FWE = 1, P14 = 0, P16 = 0, PF0 = 1 Figure 19.2 Flash Memory State Transitions Table 19.1 Differences between Boot Mode and User Program Mode Boot Mode Entire erase Block erase Programming control program* Note: Yes No Program/program-verify User Program Mode Yes Yes Program/program-verify/erase/ erase-verify/emulation * To be provided by the user, in accordance with the recommended algorithm. Rev. 1.00 Jan. 29, 2008 Page 535 of 666 REJ09B0427-0100 Section 19 ROM 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program This LSI Boot program Flash memory RAM SCI This LSI Boot program Flash memory RAM Boot program area SCI Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program This LSI Boot program Flash memory RAM Boot program area Flash memory preprogramming erase Programming control program This LSI SCI Boot program Flash memory RAM Boot program area New application program Programming control program SCI Program execution state Figure 19.3 Boot Mode Rev. 1.00 Jan. 29, 2008 Page 536 of 666 REJ09B0427-0100 Section 19 ROM 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host New application program This LSI Boot program Flash memory FWE assessment program This LSI SCI RAM Boot program Flash memory FWE assessment program SCI RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program This LSI Boot program Flash memory FWE assessment program This LSI SCI RAM Boot program Flash memory FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program SCI RAM Transfer program Flash memory erase New application program Program execution state Figure 19.4 User Program Mode (Example) Rev. 1.00 Jan. 29, 2008 Page 537 of 666 REJ09B0427-0100 Section 19 ROM 19.3 Block Configuration Figure 19.5 shows the block configuration of 384-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 4 kbytes (8 blocks), 32 kbytes (1 block), and 64 kbytes (5 blocks). Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80. Rev. 1.00 Jan. 29, 2008 Page 538 of 666 REJ09B0427-0100 Section 19 ROM EB0 Erase unit 4 kbytes EB1 Erase unit 4 kbytes EB2 Erase unit 4 kbytes EB3 Erase unit 4 kbytes EB4 Erase unit 4 kbytes EB5 Erase unit 4 kbytes EB6 Erase unit 4 kbytes EB7 Erase unit 4 kbytes EB8 Erase unit 32 kbytes EB9 Erase unit 64 kbytes EB10 Erase unit 64 kbytes EB11 Erase unit 64 kbytes EB12 Erase unit 64 kbytes EB13 Erase unit 64 kbytes H'000000 H'000F80 H'001000 H'000001 H'000F81 H'001001 H'000002 H'000F82 H'001002 Programming unit: 128 bytes H'00007F H'000FFF Programming unit: 128 bytes H'00107F H'001FFF H'001F80 H'002000 H'001F81 H'002001 H'001F82 H'002002 Programming unit: 128 bytes H'00207F H'002F80 H'003000 H'002F81 H'003001 H'002F82 H'003002 Programming unit: 128 bytes H'002FFF H'00307F H'003FFF Programming unit: 128 bytes H'00407F H'004FFF Programming unit: 128 bytes H'00507F H'005FFF Programming unit: 128 bytes H'00607F H'006FFF Programming unit: 128 bytes H'00707F H'007FFF Programming unit: 128 bytes H'00807F H'00FFFF Programming unit: 128 bytes H'01007F H'003F80 H'004000 H'004F80 H'005000 H'005F80 H'006000 H'006F80 H'007000 H'007F80 H'008000 H'003F81 H'004001 H'004F81 H'005001 H'005F81 H'006001 H'006F81 H'007001 H'007F81 H'008001 H'003F82 H'004002 H'004F82 H'005002 H'005F82 H'006002 H'006F82 H'007002 H'007F82 H'008002 H'00FF80 H'010000 H'00FF80 H'020000 H'00FF81 H'010001 H'00FF81 H'020001 H'00FF82 H'010002 H'00FF82 H'020002 Programming unit: 128 bytes H'00FFFF H'02007F H'02FFFF Programming unit: 128 bytes H'03007F H'02FF80 H'030000 H'03FF80 H'040000 H'04FF80 H'050000 H'02FF81 H'030001 H'03FF81 H'040001 H'04FF81 H'050001 H'02FF82 H'030002 H'03FF82 H'040002 H'04FF82 H'050002 Programming unit: 128 bytes Programming unit: 128 bytes H'03FFFF H'04007F H'04FFFF H'05007F H'05FFFF H'05FF80 H'05FF81 H'05FF82 Figure 19.5 Flash Memory Block Configuration Rev. 1.00 Jan. 29, 2008 Page 539 of 666 REJ09B0427-0100 Section 19 ROM 19.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 19.2. Table 19.2 Pin Configuration Pin Name RES FWE MD2 MD1 MD0 PF0 P16 P14 TxD1 RxD1 I/O Input Input Input Input Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets this LSI's operating mode Sets this LSI's operating mode Sets this LSI's operating mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Sets MCU operating mode in programmer mode Serial transmit data output Serial receive data input 19.5 Register Descriptions The flash memory has the following registers. * * * * * * Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Erase block register 2 (EBR2) RAM emulation register (RAMER) Flash memory power control register (FLPWCR) Rev. 1.00 Jan. 29, 2008 Page 540 of 666 REJ09B0427-0100 Section 19 ROM 19.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, see section 19.8, Flash Memory Programming/Erasing. Bit 7 Bit Name FWE Initial Value R/W R Description Flash Write Enable Bit Reflects the input level at the FWE pin. It is set to 1 when a low level is input to the FWE pin, and cleared to 0 when a high level is input. When this bit is cleared to 0, the flash memory changes to hardware protect mode. 6 SWE 0 R/W Software Write Enable Bit When this bit is set to 1 while FWE = 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, bits 5 to 0 in FLMCR1 and all EBR1 and EBR2 bits cannot be set. 5 ESU 0 R/W Erase Setup Bit When this bit is set to 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. Set this bit to 1 before setting the E bit in FLMCR1. 4 PSU 0 R/W Program Setup Bit When this bit is set to 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. Set this bit to 1 before setting the P bit in FLMCR1. 3 EV 0 R/W Erase-Verify When this bit is set to 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. Rev. 1.00 Jan. 29, 2008 Page 541 of 666 REJ09B0427-0100 Section 19 ROM Bit 1 Bit Name E Initial Value 0 R/W R/W Description Erase When this bit is set to 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1, and while the SWE and PSU bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled. 19.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to. Bit 7 Bit Name FLER Initial Value 0 R/W R Description Flash Memory Error Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state. See section 19.9.3, Error Protection, for details. 6 to 0 All 0 R Reserved These bits are always read as 0. Rev. 1.00 Jan. 29, 2008 Page 542 of 666 REJ09B0427-0100 Section 19 ROM 19.5.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. Bit 7 6 5 4 3 2 1 0 Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 4 kbytes of EB7 (H'007000 to H'007FFF) will be erased. When this bit is set to 1, 4 kbytes of EB6 (H'006000 to H'006FFF) will be erased. When this bit is set to 1, 4 kbytes of EB5 (H'005000 to H'005FFF) will be erased. When this bit is set to 1, 4 kbytes of EB4 (H'004000 to H'004FFF) will be erased. When this bit is set to 1, 4 kbytes of EB3 (H'003000 to H'003FFF) will be erased. When this bit is set to 1, 4 kbytes of EB2 (H'002000 to H'002FFF) will be erased. When this bit is set to 1, 4 kbytes of EB1 (H'001000 to H'001FFF) will be erased. When this bit is set to 1, 4 kbytes of EB0 (H'000000 to H'000FFF) will be erased. Rev. 1.00 Jan. 29, 2008 Page 543 of 666 REJ09B0427-0100 Section 19 ROM 19.5.4 Erase Block Register 2 (EBR2) EBR2 specifies the flash memory erase area block. EBR2 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. Bit 7, 6 5 4 3 2 1 0 Bit Name EB13 EB12 EB11 EB10 EB9 EB8 Initial Value All 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved When this bit is set to 1, 64 kbytes of EB13 (H'050000 to H'05FFFF) will be erased. When this bit is set to 1, 64 kbytes of EB12 (H'040000 to H'04FFFF) will be erased. When this bit is set to 1, 64 kbytes of EB11 (H'030000 to H'03FFFF) will be erased. When this bit is set to 1, 64 kbytes of EB10 (H'020000 to H'02FFFF) will be erased. When this bit is set to 1, 64 kbytes of EB9 (H'010000 to H'01FFFF) will be erased. When this bit is set to 1, 32 kbytes of EB8 (H'008000 to H'00FFFF) will be erased. Rev. 1.00 Jan. 29, 2008 Page 544 of 666 REJ09B0427-0100 Section 19 ROM 19.5.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER settings should be made in user mode or user program mode. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit 7, 6 5, 4 3 Bit Name RAMS Initial Value All 0 0 0 R/W R R/W R/W Description Reserved These bits are always read as 0. Reserved Always write 0 before read. RAM Select Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, the flash memory is overlapped with part of RAM, and all flash memory block are program/erase-protected. 2 1 0 RAM2 RAM1 RAM0 0 0 0 R/W R/W R/W Flash Memory Area Selection When the RAMS bit is set to 1, one of the following flash memory areas is selected to overlap the RAM area. The areas correspond with 4-kbyte erase blocks. 000: H'000000 to H'000FFF (EB0) 001: H'001000 to H'001FFF (EB1) 010: H'002000 to H'002FFF (EB2) 011: H'003000 to H'003FFF (EB3) 100: H'004000 to H'004FFF (EB4) 101: H'005000 to H'005FFF (EB5) 110: H'006000 to H'006FFF (EB6) 111: H'007000 to H'007FFF (EB7) Rev. 1.00 Jan. 29, 2008 Page 545 of 666 REJ09B0427-0100 Section 19 ROM 19.5.6 Flash Memory Power Control Register (FLPWCR) FLPWCR enables/disables transition to power-down modes for the flash memory when this LSI enters sub-active mode. Bit 7 Bit Name PDWND Initial Value 0 R/W R/W Description Power Down Disable Enables/disables transition to power-down modes for the flash memory when this LSI enters sub-active mode. 0: Transition to power-down modes for the flash memory enabled. 1: Transition to power-down modes for the flash memory disabled. 6 to 0 All 0 R Reserved These bits are always read as 0. Rev. 1.00 Jan. 29, 2008 Page 546 of 666 REJ09B0427-0100 Section 19 ROM 19.6 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19.3. For a diagram of the transitions to the various flash memory modes, see figure 19.2. Table 19.3 Setting On-Board Programming Modes Mode Setting Boot mode Expanded mode Single-chip mode User program mode Expanded mode Single-chip mode 1 FWE 1 MD2 0 0 1 1 MD1 1 1 1 1 MD0 0 1 0 1 19.6.1 Boot Mode Table 19.4 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 19.8, Flash Memory Programming/Erasing. In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. Boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. 2. SCI_1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI_1 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. Rev. 1.00 Jan. 29, 2008 Page 547 of 666 REJ09B0427-0100 Section 19 ROM 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 19.5. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFE800 to H'FFEFBF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. Before branching to the programming control program, the chip terminates transfer operations by SCI_1 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TxD pin is high. The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the FWE pin and mode pins, and executing reset release. Boot mode is also cleared when a WDT overflow occurs. 8. All interrupts are disabled during programming or erasing of the flash memory. Rev. 1.00 Jan. 29, 2008 Page 548 of 666 REJ09B0427-0100 Section 19 ROM Table 19.4 Boot Mode Operation Host Operation Processing Contents LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Bit rate adjustment Continuously transmits data H'00 at specified bit rate. H'00, H'00 ...... H'00 Item Boot mode start Communications Contents Transmits data H'55 when data H'00 is received error-free. H'00 H'55 H'AA * Measures low-level period of receive data H'00. * Calculates bit rate and sets it in BRR of SCI_1. * Transmits data H'00 to host as adjustment end indication. Transmits data H'AA to host when data H'55 is received. Receives data H'AA. Transfer of programming control program Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (lower byte following upper byte) Transmits 1-byte of programming control program (repeated for N times) Flash memory erase Boot program erase error Receives data H'AA. H'FF Upper byte and lower byte Echobacks the 2-byte data received. Echoback H'XX Echoback Echobacks received data to host and also transfers it to RAM (repeated for N times) H'AA Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Branches to programming control program transferred to on-chip RAM and starts execution. Table 19.5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate 19,200 bps 9,600 bps 4,800 bps System Clock Frequency Range of this LSI 20 MHz 8 to 20 MHz 4 to 20 MHz Rev. 1.00 Jan. 29, 2008 Page 549 of 666 REJ09B0427-0100 Section 19 ROM 19.6.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must prepare onboard means for controlling FWE, on-board means of supplying programming data, and branching conditions. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot mode. Figure 19.6 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 19.8, Flash Memory Programming/Erasing. Reset-start No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode Rev. 1.00 Jan. 29, 2008 Page 550 of 666 REJ09B0427-0100 Section 19 ROM 19.7 Flash Memory Emulation in RAM A setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. Emulation can be performed in user mode or user program mode. Figure 19.7 shows an example of emulation of real-time flash memory programming. 1. Set RAMER to overlap part of RAM onto the area for which real-time programming is required. 2. Emulation is performed using the overlapping RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing the RAM overlap. 4. The data written in the overlapping RAM is written into the flash memory space. Start of emulation program Set RAMER Write tuning data to overlap RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 19.7 Flowchart for Flash Memory Emulation in RAM Rev. 1.00 Jan. 29, 2008 Page 551 of 666 REJ09B0427-0100 Section 19 ROM An example in which flash memory block area EB0 is overlapped is shown in figure 19.8. 1. The RAM area to be overlapped is fixed at a 4-kbyte area in the range H'FFD800 to H'FFE7FF. 2. The flash memory area to be overlapped is selected by RAMER from a 4-kbyte area of the EB0 to EB7 blocks. 3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM addresses. 4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). In this state, setting the P or E bit in FLMCR1 to 1 does not cause a transition to program mode or erase mode. 5. A RAM area cannot be erased by execution of software in accordance with the erase algorithm. 6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlap RAM. Rev. 1.00 Jan. 29, 2008 Page 552 of 666 REJ09B0427-0100 Section 19 ROM H'000000 Flash memory (EB0) H'001000 (EB1) On-chip RAM (Shadow of H'FFD000 to H'FFDFFF) Flash memory (EB0) H'002000 (EB2) H'003000 (EB3) (EB3) Flash memory (EB2) H'FFD800 On-chip RAM (4 kbytes) H'FFE7FF On-chip RAM (4 kbytes) Normal memory map RAM overlap memory map Figure 19.8 Example of RAM Overlap Operation Rev. 1.00 Jan. 29, 2008 Page 553 of 666 REJ09B0427-0100 Section 19 ROM 19.8 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 19.8.1, Program/Program-Verify and section 19.8.2, Erase/Erase-Verify, respectively. 19.8.1 Program/Program-Verify When writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 19.9 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation and additional programming data computation according to figure 19.10. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Figure 19.10 shows the allowable programming times. 6. The watchdog timer (WDT) is set to prevent over-programming due to program runaway, etc. Set a value greater than (tspsu + tsp200 + tcp + tcpsu) s as the WDT overflow period. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits are B'00. Verify data can be read in words from the address to which a dummy write was performed. Rev. 1.00 Jan. 29, 2008 Page 554 of 666 REJ09B0427-0100 Section 19 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is (N). Write pulse application subroutine Start of programming START Set SWE bit in FLMCR1 Wait (tsswe) s Store 128-byte program data in program data area and reprogram data area Sub-Routine Write Pulse WDT enable Set PSU bit in FLMCR1 Wait (tspsu) s Set P bit in FLMCR1 Wait (tsp) s Clear P bit in FLMCR1 Wait (tcp) s Clear PSU bit in FLMCR1 Wait (tcpsu) s Disable WDT Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *7 *4 *7 Start of programming n=1 m=0 *5*7 End of programming Write 128-byte data in RAM reprogram data area consecutively to flash memory *1 Sub-Routine-Call *7 Write pulse See Note 6 for pulse width Set PV bit in FLMCR1 Wait (tspv) s H'FF dummy write to verify address *7 *7 Wait (tspvr) s End Sub Increment address Note: 6 Write Pulse Width Number of Writes n Write Time (tsp) sec Write data = verify data? Read verify data *7 *2 No m=1 No nn+1 1 2 3 4 5 6 7 8 9 10 11 12 13 30 30 30 30 30 30 200 200 200 200 200 200 200 Yes 6n? Yes Additional-programming data computation Transfer additional-programming data to additional-programming data area Reprogram data computation *4 *3 *4 Transfer reprogram data to reprogram data area 128-byte data verification completed? No 998 999 1000 200 200 200 Yes Clear PV bit in FLMCR1 Reprogram Wait (tcpv) s 6 n? No Note: Use a 10 s write pulse for additional programming. *7 RAM Program data storage area (128 bytes) Yes Successively write 128-byte data from additionalprogramming data area in RAM to flash memory *1 Sub-Routine-Call Write Pulse (Additional programming) Reprogram data storage area (128 bytes) m=0? Yes Clear SWE bit in FLMCR1 Wait (tcswe) s End of programming No n (N)? *7 No Additional-programming data storage area (128 bytes) Yes Clear SWE bit in FLMCR1 Wait (tcswe) s Programming failure *7 Notes: 1. 2. 3. 4. 5. 7. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Verify data is read in 16-bit (word) units. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the result of the subsequent verify operation is NG. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM. The contents of the reprogram data area and additional data area are modified as programming proceeds. A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. The wait times and value of N are shown in section 23.7, Flash Memory Characteristics. Reprogram Data Computation Table Original Data Verify Data Reprogram Data Additional-Programming Data Computation Table (X) 1 0 1 1 Still in erased state; no action Comments Programming completed Programming incomplete; reprogram (D) 0 0 1 1 (V) 0 1 0 1 Reprogram Data (X') 0 0 1 1 Verify Data Additional(V) Programming Data (Y) 0 1 0 1 0 1 1 1 Comments Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Additional programming not to be executed Figure 19.9 Program/Program-Verify Flowchart Rev. 1.00 Jan. 29, 2008 Page 555 of 666 REJ09B0427-0100 Section 19 ROM 19.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.10 should be followed. 1. Prewriting (setting erase block data to all 0) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent over-programming due to program runaway, etc. Set a value greater than (tsesu + tse + tce + tcesu) ms as the WDT overflow period. 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in words from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is (N). 19.8.3 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. Interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. Rev. 1.00 Jan. 29, 2008 Page 556 of 666 REJ09B0427-0100 Section 19 ROM Start *1 Perform erasing in block units. Set SWE bit in FLMCR1 Wait (tsswe) s n=1 Set EBR1 or EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (tsesu) s Set E bit in FLMCR1 Wait (tse) ms Clear E bit in FLMCR1 Wait (tce) s Clear ESU bit in FLMCR1 Wait (tcesu) s Disable WDT Set EV bit in FLMCR1 Wait (tsev) s Set block start address as verify address *5 *5 *5 *3 *4 *5 Start of erase *5 Erase halted *5 nn+1 H'FF dummy write to verify address Wait (tsevr) s Increment address Read verify data Verify data = all 1s? Yes No Last address of block? Yes Clear EV bit in FLMCR1 Wait (tcev) s Clear EV bit in FLMCR1 Wait (tcev) s *5 *5 *2 No *5 *5 n (N)? Clear SWE bit in FLMCR1 Wait (tcswe) s End of erasing *5 No Yes Clear SWE bit in FLMCR1 Wait (tcswe) s Erase failure *5 Notes: 1. 2. 3. 4. 5. Prewriting (setting erase block data to all 0s) is not necessary. Verify data is read in 16-bit (word) units. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). Two or more bits must not be set simultaneously. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. The wait times and the value of N are shown in section 23.7, Flash Memory Characteristics. Figure 19.10 Erase/Erase-Verify Flowchart Rev. 1.00 Jan. 29, 2008 Page 557 of 666 REJ09B0427-0100 Section 19 ROM 19.9 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 19.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2) are initialized. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. 19.9.2 Software Protection Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register 1 and 2 (EBR1 and EBR2), erase protection can be set for individual blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks. By setting bit RAMS in RAMER, programming/erase protection is set for all blocks. 19.9.3 Error Protection In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to over-programming or over-erasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling (excluding a reset) during programming/erasing * When a SLEEP instruction is executed during programming/erasing * When the CPU loses the bus during programming/erasing Rev. 1.00 Jan. 29, 2008 Page 558 of 666 REJ09B0427-0100 Section 19 ROM The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a reset or in hardware standby. 19.10 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input, are disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in CPU runaway. 3. If an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. Notes: 1. Interrupt requests must be disabled inside and outside the CPU until the programming control program has completed programming. 2. The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). * If the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. Rev. 1.00 Jan. 29, 2008 Page 559 of 666 REJ09B0427-0100 Section 19 ROM 19.11 Programmer Mode In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the Renesas 256-kbyte flash memory on-chip microcomputer device type (FZTAT256V5A). 19.12 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: * Normal operating mode The flash memory can be read and written to at high speed. * Power-down state The flash memory can be read when part of the power circuit is halted and the LSI operates by subclocks. * Standby mode All flash memory circuits are halted. Table 19.6 shows the correspondence between the operating modes of this LSI and the flash memory. When the flash memory returns to its normal operating state from standby mode, a period to stabilize the power supply circuits that were stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 100 s, even when the external clock is being used. Table 19.6 Flash Memory Operating States LSI Operating State Active mode Sleep mode Watch mode Standby mode Sub-active mode Sub-sleep mode PDWND = 0: Power-down mode (read only) PDWND = 1: Normal operating mode (read only) Flash Memory Operating State Normal operating mode Normal operating mode Standby mode Rev. 1.00 Jan. 29, 2008 Page 560 of 666 REJ09B0427-0100 Section 19 ROM 19.13 Usage Notes Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Only use the specified socket adapter. Failure to observe these points may result in damage to the device. Powering on and off: Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low before turning off VCC. When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory in the hardware protection state. The power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. FWE application/disconnection: FWE application should be carried out when MCU operation is in a stable condition. If MCU operation is not stable, fix the FWE pin low and set the protection state. The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: * Apply FWE when the VCC voltage has stabilized within its rated voltage range. * In boot mode, apply and disconnect FWE during a reset. * In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during execution of a program in flash memory. * Do not apply FWE if program runaway has occurred. * Disconnect FWE only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 are cleared. Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying or disconnecting FWE. Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent over-programming or over-erasing due to program runaway, etc. Rev. 1.00 Jan. 29, 2008 Page 561 of 666 REJ09B0427-0100 Section 19 ROM Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Do not set or clear the SWE bit during execution of a program in flash memory: Wait for at least 100 s after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function while a high level is being input to the FWE pin, the SWE bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In onboard programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer: Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming: Touching either of these can cause contact faults and write errors. Reset the flash memory before turning on the power: To reset the flash memory during oscillation stabilization period, the reset signal must be input for at least 100 s. Apply the reset signal while SWE is low to reset the flash memory during its operation: The reset signal is applied at least 100 s after the SWE bit has been cleared. Rev. 1.00 Jan. 29, 2008 Page 562 of 666 REJ09B0427-0100 Section 19 ROM Note on Switching from F-ZTAT Version to Mask ROM Version: The mask ROM version does not have the internal registers for flash memory control that are provided in the F-ZTAT version. Table 19.7 lists the registers that are present in the F-ZTAT version but not in the mask ROM version. If a register listed in table 19.7 is read in the mask ROM version, an undefined value will be returned. Therefore, if application software developed on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure that the registers in table 19.7 have no effect. Table 19.7 Registers Present in F-ZTAT Version but Absent in Mask ROM Version Register Flash memory control register 1 Flash memory control register 2 Erase block register 1 RAM emulation register Flash memory power control register Abbreviation FLMCR1 FLMCR2 EBR1 RAMER FLPWCR Address H'FFA8 H'FFA9 H'FFAA FFAB FEDB Rev. 1.00 Jan. 29, 2008 Page 563 of 666 REJ09B0427-0100 Section 19 ROM Rev. 1.00 Jan. 29, 2008 Page 564 of 666 REJ09B0427-0100 Section 20 Clock Pulse Generator Section 20 Clock Pulse Generator This LSI has an on-chip clock pulse generator that generates the system clock (), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL circuit, clock selection circuit, medium-speed clock divider, and bus master clock selection circuit. A block diagram of the clock pulse generator is shown in figure 20.1. LPWRCR STC0, STC1 SCKCR SCK2 to SCK0 EXTAL XTAL System clock oscillator PLL circuit (x1, x2, x4) Clock selection circuit SUB Mediumspeed clock divider /2 to /32 Bus master clock selection circuit OSC1 OSC2 Subclock oscillator Waveform generation circuit System clock to pin Internal clock to peripheral modules Bus master clock to CPU and DTC WDT_1 count clock [Legend] LPWRCR: Low-power control register SCKCR: System clock control register Figure 20.1 Block Diagram of Clock Pulse Generator The frequency can be changed by means of the PLL circuit. Frequency changes are performed by software by settings in the low-power control register (LPWRCR) and system clock control register (SCKCR). Rev. 1.00 Jan. 29, 2008 Page 565 of 666 REJ09B0427-0100 Section 20 Clock Pulse Generator 20.1 Register Descriptions The on-chip clock pulse generator has the following registers. For details on LPWRCR, see section 21.1.2, Low-Power Control Register (LPWRCR). * System clock control register (SCKCR) * Low-power control register (LPWRCR) 20.1.1 System Clock Control Register (SCKCR) SCKCR performs clock output control, selection of operation when the PLL circuit frequency multiplication factor is changed, and medium-speed mode control. Bit 7 Bit Name PSTOP Initial Value 0 R/W R/W Description Clock Output Disable Controls output. High-speed Mode, Medium-Speed Mode 0: output 1: Fixed high Sleep Mode 0: output 1: Fixed high Software Standby Mode 0: Fixed high 1: Fixed high Hardware Standby Mode 0: High impedance 1: High impedance 6 to 4 All 0 Reserved These bits are always read as 0. Rev. 1.00 Jan. 29, 2008 Page 566 of 666 REJ09B0427-0100 Section 20 Clock Pulse Generator Bit 3 Bit Name STCS Initial Value 0 R/W R/W Description Frequency Multiplication Factor Switching Mode Select Selects the operation when the PLL circuit frequency multiplication factor is changed. 0: Specified multiplication factor is valid after transition to software standby mode 1: Specified multiplication factor is valid immediately after STC1 bit and STC0 bit are rewritten 2 1 0 SCK2 SCK1 SCK0 0 0 0 R/W R/W R/W System Clock Select 0 to 2 These bits select the bus master clock. 000: High-speed mode 001: Medium-speed clock is /2 010: Medium-speed clock is /4 011: Medium-speed clock is /8 100: Medium-speed clock is /16 101: Medium-speed clock is /32 11X: Setting prohibited [Legend] X: Don't care Rev. 1.00 Jan. 29, 2008 Page 567 of 666 REJ09B0427-0100 Section 20 Clock Pulse Generator 20.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. In either case, the input clock should not exceed 20 MHz. 20.2.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 20.2. Select the damping resistance Rd according to table 20.1. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22 pF Figure 20.2 Connection of Crystal Resonator (Example) Table 20.1 Damping Resistance Value Frequency (MHz) Rd () 4 500 8 200 10 0 12 0 16 0 20 0 Figure 20.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 20.2. CL XTAL L Rs EXTAL C0 AT-cut parallel-resonance type Figure 20.3 Crystal Resonator Equivalent Circuit Rev. 1.00 Jan. 29, 2008 Page 568 of 666 REJ09B0427-0100 Section 20 Clock Pulse Generator Table 20.2 Crystal Resonator Characteristics Frequency (MHz) RS max () C0 max (pF) 4 120 7 8 80 7 10 70 7 12 60 7 16 50 7 20 40 7 20.2.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 20.4. If the XTAL pin is left open, ensure that stray capacitance does not exceed 10 pF. When complementary clock is input to the XTAL pin, the external clock input should be fixed high in standby mode. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin Figure 20.4 External Clock Input (Examples) Rev. 1.00 Jan. 29, 2008 Page 569 of 666 REJ09B0427-0100 Section 20 Clock Pulse Generator Table 20.3 shows the input conditions for the external clock. Table 20.3 External Clock Input Conditions VCC = 5.0 V 10% Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Symbol tEXL tEXH tEXr tEXf Min. 15 15 Max. 5 5 Unit ns ns ns ns Test Conditions Figure 20.5 tEXH tEXL VCC x 0.5 EXTAL tEXr tEXf Figure 20.5 External Clock Input Timing Rev. 1.00 Jan. 29, 2008 Page 570 of 666 REJ09B0427-0100 Section 20 Clock Pulse Generator 20.3 PLL Circuit The PLL circuit multiplies the frequency of the clock from the oscillator by a factor of 1, 2, or 4. The multiplication factor is set by the STC0 bit and the STC1 bit in LPWRCR. The phase of the rising edge of the internal clock is controlled so as to match that at the EXTAL pin. When the multiplication factor of the PLL circuit is changed, the operation varies according to the setting of the STCS bit in SCKCR. When STCS = 0, the setting becomes valid after a transition to software standby mode. The transition time count is performed in accordance with the setting of bits STS0 to STS2 in SBYCR. For details on SBYCR, see section 21.1.1, Standby Control Register (SBYCR). 1. 2. 3. 4. 5. The initial PLL circuit multiplication factor is 1. STS0 to STS2 are set to give the specified transition time. The target value is set in STC0 and STC1, and a transition is made to software standby mode. The clock pulse generator stops and the value set in STC0 and STC1 becomes valid. Software standby mode is cleared, and a transition time is secured in accordance with the setting in STS0 to STS2. 6. After the set transition time has elapsed, this LSI resumes operation using the target multiplication factor. If a PC break is set for the SLEEP instruction, software standby mode is entered and break exception handling is executed after the oscillation settling time. In this case, the instruction following the SLEEP instruction is executed after execution of the RTE instruction. When STCS = 1, this LSI operates on the changed multiplication factor immediately after bits STC0 and STC1 are rewritten. 20.4 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32. 20.5 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the clock supplied to the bus master by setting the bits SCK 2 to 0 in SCKCR. The bus master clock can be selected from high-speed mode, or medium-speed clocks (/2, /4, /8, /16, /32). Rev. 1.00 Jan. 29, 2008 Page 571 of 666 REJ09B0427-0100 Section 20 Clock Pulse Generator 20.6 20.6.1 Subclock Oscillator Connecting 32.768-kHz Crystal Resonator To supply a clock to the subclock divider, connect a 32.768-kHz crystal resonator, as shown in figure 20.6. Concerning the note on connection, see section 20.8.2, Note on Board Design. C1 OSC1 C2 OSC2 C1 = C2 = 15pF (typ) * Note: * C1 and C2 are reference values including the floating capacitance of the boad. Figure 20.6 Connection Example of 32.768-kHz Crystal Resonator Figure 20.7 shows the equivalent circuit for a 32.768-kHz crystal resonator. Ls Cs Rs OSC1 Co OSC2 Figure 20.7 Equivalent Circuit for 32.768-kHz Crystal Resonator Rev. 1.00 Jan. 29, 2008 Page 572 of 666 REJ09B0427-0100 Section 20 Clock Pulse Generator 20.6.2 Handling Pins when Subclock is not Used If no subclock is required, connect the OSC1 pin to Vss and leave the OSC2 pin open, as shown in figure 20.8. OSC1 OSC2 Open Figure 20.8 Pin Handling when Subclock is not Used 20.7 Subclock Waveform Generation Circuit To eliminate noise from the subclock input from the OSC1 pin, the subclock is sampled using the dividing clock . The sampling frequency is set using the NESEL bit in LPWRCR. For details, see section 21.1.2, Low-Power Control Register (LPWRCR). No sampling is performed in subactive, subsleep, and watch mode. 20.8 20.8.1 Usage Notes Note on Crystal Resonator As various characteristics related to the crystal resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a guide. As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. Rev. 1.00 Jan. 29, 2008 Page 573 of 666 REJ09B0427-0100 Section 20 Clock Pulse Generator 20.8.2 Note on Board Design When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator circuit, as shown in figure 20.9. This is to prevent induction from interfering with correct oscillation. Avoid CL2 Signal A Signal B This LSI XTAL EXTAL CL1 Figure 20.9 Note on Board Design of Oscillator Circuit Figure 20.10 shows external circuitry recommended to be provided around the PLL circuit. Place oscillation settling capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Separate PLLVss from the other Vcc and Vss lines at the board power supply source, and be sure to insert bypass capacitors CB close to the pins. R1 : 3 k C1 : 470 pF PLLCAP PLLVSS VCL VCC CB : 0.1 F* CB : 0.1 F VSS (Values are preliminary recommended values.) Note: * CB is laminated ceramic. Figure 20.10 External Circuitry Recommended for PLL Circuit Rev. 1.00 Jan. 29, 2008 Page 574 of 666 REJ09B0427-0100 Section 21 Power-Down Modes Section 21 Power-Down Modes In addition to the normal program execution state, this LSI has power-down modes in which operation of the CPU and oscillator is halted and power consumption is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on. This LSI's operating modes are as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. High-speed mode Medium-speed mode Subactive mode Sleep mode Subsleep mode Watch mode Module stop mode Software standby mode Hardware standby mode Modes 2. to 9. are power-down modes. Sleep mode and subsleep mode are CPU states, mediumspeed mode is a CPU and bus master state, subactive mode is a CPU, bus master, and on-chip peripheral function state, and module stop mode is an on-chip peripheral function (including bus masters other than the CPU) state. Some of these states can be combined. After a reset, the LSI operates in high-speed mode with on-chip peripheral modules other than the DTC in module stop mode. Table 21.1 shows the internal state of the LSI in each mode. Table 21.2 shows the conditions for shifting between the power-down modes. Figure 21.1 shows the mode transition diagram. Rev. 1.00 Jan. 29, 2008 Page 575 of 666 REJ09B0427-0100 Section 21 Power-Down Modes Table 21.1 LSI Internal States in Each Mode HighFunction System clock pulse generator Subclock generator CPU Speed MediumSpeed Sleep Module Stop Watch Subactive Halted Subsleep Halted Software Standby Halted Hardware Standby Halted Functioning Functioning Functioning Functioning Halted Functioning Functioning Functioning Functioning Functioning Halted (retained) High/ mediumspeed operation Halted (retained) Functioning Subclock operation Functioning Halted (retained) Halted Halted (retained) Halted Halted (undefined) Instructions Functioning MediumRegisters speed operation External interrupts NMI IRQ0 to IRQ5 Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted Peripheral functions WDT0 Functioning Functioning Functioning Functioning Functioning Functioning Halted (retained) Subclock operation Subclock operation Halted (retained) Subclock operation Subclock operation Halted (retained) Halted (retained) Halted (retained) Halted (retained) Halted (reset) Halted (reset) Halted (reset) WDT1 Subclock operation DTC Functioning Mediumspeed operation Functioning Halted (retained) Halted (retained) TPU PPG IIC_0 IIC_1 DA_1,0 PBC Functioning Functioning Functioning Halted (retained) Halted (retained) Halted (retained) Halted (retained) Halted (retained) Halted (reset) Functioning Functioning Functioning Halted (retained) Halted (retained) Halted (retained/ reset) Halted (reset) Subclock operation Halted (retained/ reset) Halted (reset) Functioning Halted (retained) Halted (retained/ reset) Halted (reset) Retained Halted (retained) Halted (reset) Halted (reset) Halted (reset) SCI0 to SCI2 SCI4 PWM A/D RAM Functioning Functioning Functioning Halted (retained/ reset) Functioning Functioning Functioning Halted (reset) Halted (reset) Retained Halted (reset) Retained Functioning Functioning Functioning Functioning Retained (DTC) I/O Functioning Functioning Functioning Functioning Retained Functioning Retained Retained High impedance Notes: "Halted (retained)" means that internal register values are retained. The internal state is "operation suspended. " "Halted (reset)" means that internal register values and internal states are initialized. In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). Rev. 1.00 Jan. 29, 2008 Page 576 of 666 REJ09B0427-0100 Section 21 Power-Down Modes Program-halted state STBY pin = Low Reset state STBY pin = High RES pin = Low Program execution state RES pin = High SSBY= 0, LSON= 0 SLEEP instruction High-speed mode (main clock) Any interrupt *3 SCK2 to SCK0= 0 SCK2 to SCK0 0 SLEEP instruction External interrupt *4 SLEEP instruction Interrupt *1 LSON bit = 0 SLEEP instruction SSBY = 1, PSS = 1 DTON = 1, LSON = 0 After the oscillation stabilization time (STS2 to STS0), clock switching exception handling SLEEP instruction SSBY = 1, PSS = 1 DTON = 1, LSON = 1 Clock switching exception handling SSBY= 1, PSS= 1, DTON= 0 Watch mode (subclock) SSBY= 1, PSS= 0, LSON= 0 Software standby mode Sleep mode (main clock) Hardware standby mode Medium-speed mode (main clock) SLEEP instruction Interrupt *1 LSON bit = 1 SLEEP instruction Interrupt *2 SSBY= 0, PSS= 1, LSON= 1 Subsleep mode (subclock) Subactive mode (subclock) : Transition after exception processing Notes: 1. 2. 3. 4. : Power-down mode NMI, IRQ0 to IRQ5, and WDT1 interrupts NMI, IRQ0 to IRQ5, IWDT0 interrupts, and WDT1 interrupts. All interrupts NMI and IRQ0 to IRQ5 * When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. * From any state except hardware standby mode, a transition to the reset state occurs when RES is driven low. * From any state, a transition to hardware standby mode occurs when STBY is driven low. * Always select high-speed mode before making a transition to watch mode or subactive mode. Figure 21.1 Mode Transition Diagram Rev. 1.00 Jan. 29, 2008 Page 577 of 666 REJ09B0427-0100 Section 21 Power-Down Modes Table 21.2 Power-Down Mode Transition Conditions PreTransition State Status of Control Bit at Transition SSBY PSS X X 0 0 1 1 1 1 0 1 1 0 1 1 1 1 LSON 0 1 0 1 0 1 0 1 X 0 1 X 0 1 0 1 DTON X X X X 0 0 1 1 X X X X 0 0 1 1 State after Transition Invoked by SLEEP Instruction Sleep Software standby Watch Watch Subactive Subsleep Watch Watch High-speed State after Transition back from PowerDown Mode Invoked by Interrupt High-speed/mediumspeed High-speed/mediumspeed High-speed Subactive Subactive High-speed Subactive High-speed/ 0 mediumspeed 0 1 1 1 1 1 1 Subactive 0 0 0 1 1 1 1 1 [Legend] X: Don't care : Setting prohibited Rev. 1.00 Jan. 29, 2008 Page 578 of 666 REJ09B0427-0100 Section 21 Power-Down Modes 21.1 Register Descriptions Registers related to power-down modes are shown below. For details on SCKCR, see section 20.1.1, System Clock Control Register (SCKCR). For details on TCSR, see section 12.2.2, Timer Control/Status Register (TCSR). * * * * * * * * Standby control register (SBYCR) System clock control register (SCKCR) Low-power control register (LPWRCR) Timer control/status register (TCSR) Module stop control register A (MSTPCRA) Module stop control register B (MSTPCRB) Module stop control register C (MSTPCRC) Module stop control register D (MSTPCRD) Standby Control Register (SBYCR) 21.1.1 SBYCR controls power-down modes. Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby This bit in combination with other control bits specifies the operating mode after executing the SLEEP instruction. For details, see table 21.2. 0: Shifts to sleep mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode, or to subsleep mode when the SLEEP instruction is executed in subactive mode 1: Shifts to software standby mode, subactive mode, or watch mode when the SLEEP instruction is executed in high-speed mode or medium-speed mode, or to watch mode or high-speed mode when the SLEEP instruction is executed in subactive mode This bit does not change when shifting between modes by using interrupts. 0 should be written to this bit to clear it. Rev. 1.00 Jan. 29, 2008 Page 579 of 666 REJ09B0427-0100 Section 21 Power-Down Modes Bit 6 5 4 Bit Name STS2 STS1 STS0 Initial Value 0 0 0 R/W R/W R/W R/W Description Standby Timer Select These bits select the MCU standby time for clock stabilization when software standby mode, watch mode, or subactive mode is canceled by an interrupt or an instruction to shift to high-speed mode or mediumspeed mode. With a crystal resonator (table 21.3), select a standby time of 8 ms (oscillation stabilization time) or more, depending on the operating frequency. With an external clock, any standby time can be selected. 000: Standby time = 8192 states 001: Standby time = 16384 states 010: Standby time = 32768 states 011: Standby time = 65536 states 100: Standby time = 131072 states 101: Standby time = 262144 states 110: Reserved 111: Standby time = 16 states 3 OPE 1 R/W Output Port Enable Specifies whether the outputs of the address bus and bus control signals (AS, RD, HWR, LWR) are retained or set to high-impedance state in software standby mode or watch mode, or when making a direct transition. 2 to 0 -- All 0 -- Reserved These bits are always read as 0 and cannot be modified. Rev. 1.00 Jan. 29, 2008 Page 580 of 666 REJ09B0427-0100 Section 21 Power-Down Modes * With Crystal Resonator The STS2 to STS0 bits must be specified appropriately so that the standby time (oscillation stabilization time) is at least 8 ms. Table 21.3 shows the standby time determined by a combination of the operating frequency and the STS2 to STS0 bit setting. Table 21.3 Standby Time Settings Operating Frequency (MHz) STS2 0 0 0 0 1 1 1 1 STS1 0 0 1 1 0 0 1 1 STS0 0 1 0 1 0 1 0 1 Standby Time 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states* 20 0.41 0.82 1.6 3.3 6.6 13.1 -- 0.8 16 0.51 1.0 2.0 4.1 8.2 16.4 -- 1.0 12 0.65 1.3 2.7 5.5 10.9 21.8 -- 1.3 10 0.8 1.6 3.3 6.6 13.1 26.2 -- 1.6 8 1.0 2.0 4.1 8.2 16.4 32.8 -- 2.0 6 1.3 2.7 5.5 10.9 21.8 43.6 -- 1.7 4 2.0 4.1 8.2 16.4 32.8 65.6 -- 4.0 s ms Unit Notes: * : Recommended standby time Setting prohibited * With External Clock The PLL circuit stabilization time must be ensured. Specify 2-ms or more standby time. Rev. 1.00 Jan. 29, 2008 Page 581 of 666 REJ09B0427-0100 Section 21 Power-Down Modes 21.1.2 Low-Power Control Register (LPWRCR) LPWRCR controls power-down modes. Bit 7 Bit Name DTON Initial Value 0 R/W R/W Description Direct Transition ON Flag This bit in combination with the SSBY bit in SBYCR, the LSON bit in LPWRCR, and the PSS bit in TCSR specifies the operating mode after executing the SLEEP instruction. For details, see table 21.2. 6 LSON 0 R/W Low-Speed ON Flag This bit in combination with the SSBY bit in SBYCR, the DTON bit in LPWRCR, and the PSS bit in TCSR specifies the operating mode after executing the SLEEP instruction. For details, see table 21.2. 5 NESEL 0 R/W Noise Elimination Sampling Frequency Select Selects the frequency of the clock () generated by the system clock oscillator to be used to sample the subclock (SUB) generated by the subclock oscillator. Set this bit to 0 when is 5 MHz or larger. 0: Sampled at /32 1: Sampled at /4 4 SUBSTP 0 R/W Subclock Enable Enables or disables subclock generation 0: Enables subclock generation 1: Disables subclock generation 3 RFCUT 0 R/W Oscillation Circuit Feedback Resistance Control Turns the internal feedback resistance of the main clock oscillator on or off. 0: When the main clock is oscillating, sets the feedback resistance on. When the main clock is stopped, sets the feedback resistance off. 1: Sets the feedback resistance off. Rev. 1.00 Jan. 29, 2008 Page 582 of 666 REJ09B0427-0100 Section 21 Power-Down Modes Bit 2 1 0 Bit Name STC1 STC0 Initial Value 0 0 0 R/W R/W R/W R/W Description Reserved The write value should always be 0. Frequency Multiplication Factor These bits specify the frequency multiplication factor of the PLL circuit. 00: x1 01: x2 10: x4 11: Setting prohibited The peripheral clock frequency after the frequency multiplication should not be set beyond the maximum operating frequency of this LSI. Lowering the external clock peripheral frequency with this PLLx4, the current consumption and noise can be eliminated. 21.1.3 Module Stop Control Registers A to D (MSTPCRA to MSTPCRD) MSTPCR controls module stop mode. Setting a bit to 1 causes the corresponding module to enter module stop mode. Clearing the bit to 0 clears the module stop mode. * MSTPCRA Bit 7 6 5 4 3 2 1 0 Bit Name MSTPA7* MSTPA6 MSTPA5 MSTPA4* MSTPA3 MSTPA2 MSTPA1 MSTPA0* 2 2 1 Initial Value 0 0 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Module Data transfer controller (DTC) 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG) D/A converter A/D converter Rev. 1.00 Jan. 29, 2008 Page 583 of 666 REJ09B0427-0100 Section 21 Power-Down Modes * MSTPCRB Bit 7 6 5 4 3 2 1 0 Bit Name MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2*2 MSTPB1* 2 Initial Value 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Module Serial communication interface_0 (SCI_0) Serial communication interface_1 (SCI_1) Serial communication interface_2 (SCI_2) I2C bus interface_0 (IIC_0) I2C bus interface_1 (IIC_1) MSTPB0*2 * MSTPCRC Bit 7 6 5 4 3 2 1 0 Bit Name MSTPC7* MSTPC6* 2 2 Initial Value 1 1 1 1 2 R/W R/W R/W R/W R/W R/W R/W R/W R/W Module MSTPC5*2 MSTPC4 MSTPC3* MSTPC2* MSTPC1* MSTPC0* 2 PC break controller (PBC) 1 1 1 1 2 2 Rev. 1.00 Jan. 29, 2008 Page 584 of 666 REJ09B0427-0100 Section 21 Power-Down Modes * MSTPCRD Bit 7 6 5 4 3 2 1 0 Bit Name MSTPD7 MSTPD6* MSTPD5* MSTPD4* MSTPD3* MSTPD2* MSTPD1* 2 3 Initial Value 1 1 R/W R/W R/W Module Motor control PWM timer (PWM) Undefined 1 R/W Undefined 1 R/W Undefined Undefined 2 3 2 3 MSTPD0*3 Notes: 1. Although this bit is readable/writable, only 0 should be written to. 2. Although this bit is readable/writable, only 1 should be written to. 3. This bit is read as undefined value and cannot be modified. 21.2 Medium-Speed Mode When the SCK2 to SCK0 bits in SCKCR are set to 1 in high-speed mode, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (/2, /4, /8, /16, or /32) specified by the SCK2 to SCK0 bits. The bus master (DTC) other than the CPU operates in medium-speed mode. On-chip peripheral modules other than the bus masters always operate on the high-speed clock (). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip memory is accessed in four states, and internal I/O registers in eight states. Medium-speed mode is canceled by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is canceled at the end of the current bus cycle. If the SLEEP instruction is executed when the SSBY bit in SBYCR = 0 and LSON bit in LPWRCR = 0, a transition is made to sleep mode. When sleep mode is canceled by an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the SSBY bit = 1, LSON bit in LPWRCR = 0, and PSS bit in TCSR (WDT1) = 0, operation shifts to software standby mode. When software standby mode is canceled by an external interrupt, medium-speed mode is restored. Rev. 1.00 Jan. 29, 2008 Page 585 of 666 REJ09B0427-0100 Section 21 Power-Down Modes When the RES pin is driven low and medium-speed mode is canceled, operation shifts to the reset state. The same applies to a reset caused by an overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 21.2 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode , peripheral module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 21.2 Medium-Speed Mode Transition and Clearance Timing 21.3 Sleep Mode When the SLEEP instruction is executed when the SSBY bit in SBYCR = 0 and the LSON bit in LPWRCR = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other peripheral modules do not stop. Sleep mode is canceled by any interrupt, or signals at the RES or STBY pin. When an interrupt occurs, sleep mode is canceled and interrupt exception handling starts. Sleep mode is not canceled if the interrupt is disabled, or if interrupts other than NMI are masked by the CPU. When the RES pin is driven low, operation shifts to the reset state. After the stipulated reset input duration, driving the RES pin high makes the CPU start reset exception handling. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 1.00 Jan. 29, 2008 Page 586 of 666 REJ09B0427-0100 Section 21 Power-Down Modes 21.4 Software Standby Mode When the SLEEP instruction is executed when the SSBY bit in SBYCR = 1, the LSON bit in LPWRCR = 0, and the PSS bit in TCSR (WDT1) = 0, a transition is made to software standby mode. In this mode, the CPU, on-chip peripheral modules, and oscillator all stop. However, the contents of the CPU internal registers and on-chip RAM data, the states of on-chip peripheral modules other than the SCI, A/D converter, and motor control PWM, and the states of I/O ports are retained. The address bus and bus control signals are placed in the high-impedance state. Software standby mode is canceled by an external interrupt (NMI and IRQ5 to IRQ0 pins), or signals at the RES pin or STBY pin. When an NMI or IRQ5 to IRQ0 interrupt request signal is input, clock oscillation starts, and after the time set in bits STS2 to STS0 in SBYCR has elapsed, stable clocks are supplied to the entire chip, software standby mode is canceled, and interrupt exception handling is started. When canceling software standby mode with an IRQ5 to IRQ0 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ5 to IRQ0 is generated. Software standby mode cannot be canceled if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. When the RES pin is driven low, clock oscillation starts. At the same time as clock oscillation starts, the clock is supplied to the entire chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin is driven high, the CPU begins reset exception handling. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 21.3 shows an example in which a transition is made to software standby mode at a falling edge of the NMI pin, and software standby mode is canceled at a rising edge of the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then canceled at the rising edge of the NMI pin. Rev. 1.00 Jan. 29, 2008 Page 587 of 666 REJ09B0427-0100 Section 21 Power-Down Modes Oscillator NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG=1 SSBY=1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 21.3 Software Standby Mode Application Example Rev. 1.00 Jan. 29, 2008 Page 588 of 666 REJ09B0427-0100 Section 21 Power-Down Modes 21.5 Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption. As long as the prescribed voltage is supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 and MD0) while this LSI is in hardware standby mode. Hardware standby mode is canceled by signals at the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is entered and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms (oscillation stabilization time) when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is canceled by driving the STBY pin high, waiting for the oscillation stabilization time, then switching the RES pin from low to high. Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 21.4 Hardware Standby Mode Timing Rev. 1.00 Jan. 29, 2008 Page 589 of 666 REJ09B0427-0100 Section 21 Power-Down Modes 21.6 Watch Mode When the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 0, and the PSS bit in TCSR (WDT1) = 1, CPU operation shifts to watch mode. In watch mode, the CPU stops and peripheral modules other than WDT1 also stop. The contents of the CPU internal registers and on-chip RAM data, the states of on-chip peripheral modules other than the SCI, A/D converter, and motor control PWM, and the states of I/O ports are retained. Watch mode is canceled by any interrupt (WOVI1 interrupt, NMI pin, or IRQ5 to IRQ0 pins), or signals at the RES or STBY pin. When an interrupt occurs, watch mode is canceled and a transition is made to high-speed mode or medium-speed mode when the LSON bit in LPWRCR = 0 or to subactive mode when the LSON bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to the entire LSI and interrupt exception handling starts after the time set in the STS2 to STS0 bits of SBYCR has elapsed. For an IRQ5 to IRQ0 interrupt, watch mode is not canceled if the corresponding enable bit has been cleared to 0. For an interrupt from an on-chip peripheral module, if the interrupt enable register has been set to disable the reception of that interrupt or is masked by the CPU, watch mode is not canceled. For the setting of the oscillation stabilization time when making a transition from watch mode to high-speed mode, see table 21.3. For canceling watch mode by the RES pin, see section 21.4, Software Standby Mode. When the STBY pin is driven low, a transition is made to hardware standby mode. Rev. 1.00 Jan. 29, 2008 Page 590 of 666 REJ09B0427-0100 Section 21 Power-Down Modes 21.7 Subsleep Mode When the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR = 0, the LSON bit in LPWRCR = 1, and the PSS bit in TCSR (WDT1) = 1, CPU operation shifts to subsleep mode. In subsleep mode, the CPU stops and peripheral modules other than WDT0 and WDT1 also stop. The contents of the CPU internal registers and on-chip RAM data, and the states of on-chip peripheral modules other than the SCI, A/D converter, and motor control PWM, and the states of I/O ports are retained. Subsleep mode is canceled by any interrupt (interrupts from on-chip peripheral modules, NMI pin, or IRQ5 to IRQ0 pins), or signals at the RES or STBY pin. When an interrupt occurs, subsleep mode is canceled and interrupt exception handling starts. For an IRQ5 to IRQ0 interrupt, subsleep mode is not canceled if the corresponding enable bit has been cleared to 0. For an interrupt from an on-chip peripheral module, if the interrupt enable register has been set to disable the reception of that interrupt or is masked by the CPU, subsleep mode is not canceled. For canceling subsleep mode by the RES pin, see section 21.4, Software Standby Mode. When the STBY pin is driven low, a transition is made to hardware standby mode. 21.8 Subactive Mode CPU operation shifts to subactive mode when the SLEEP instruction is executed in high-speed mode with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1, the LSON bit = 1, and the PSS bit in TCSR (WDT1) = 1. When an interrupt occurs in watch mode, and if the LSON bit in LPWRCR is 1, a transition is made to subactive mode. If an interrupt occurs in subsleep mode, a transition is made to subactive mode. In subactive mode, the CPU operates at low speed on the subclock, and the program is executed one after another. Peripheral modules other than WDT0 and WDT1 are also stopped. When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SCKCR must be set to 0. Subactive mode is canceled by the SLEEP instruction or signals at the RES or STBY pin. Rev. 1.00 Jan. 29, 2008 Page 591 of 666 REJ09B0427-0100 Section 21 Power-Down Modes When the SLEEP instruction is executed with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 0, and the PSS bit in TCSR (WDT1) = 1, subactive mode is canceled and a transition is made to watch mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR = 0, the LSON bit in LPWRCR = 1, and the PSS bit in TCSR (WDT1) = 1, a transition is made to subsleep mode. When the SLEEP instruction is executed with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1, the LSON bit = 0, and the PSS bit in TCSR (WDT1) = 1, a direct transition is made to high-speed mode (SCK0 to SCK2 are all 0). For details on direct transitions, see section 21.10, Direct Transitions. For canceling subactive mode by the RES pin, see section 21.4, Software Standby Mode. When the STBY pin is driven low, a transition is made to hardware standby mode. 21.9 Module Stop Mode Module stop mode can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 21.4 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is canceled and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI*, motor control PWM, and A/D converter are retained. After reset clearance, all modules other than DTC are in module stop mode. When an on-chip peripheral module is in module stop mode, read/write access to its registers is disabled. Note * Internal states in some part of registers in SCI are retained. Rev. 1.00 Jan. 29, 2008 Page 592 of 666 REJ09B0427-0100 Section 21 Power-Down Modes 21.10 Direct Transitions 21.10.1 Overview of Direct Transitions There are three modes, high-speed, medium-speed, and subactive, in which the CPU executes programs. When a direct transition is made, there is no interruption of program execution in shifting between high-speed and subactive modes. Direct transitions are enabled by setting the DTON bit in LPWRCR to 1, then executing the SLEEP instruction. After a transition, direct transition interrupt exception handling starts. Direct Transition from High-Speed Mode to Subactive Mode: Execute the SLEEP instruction in high-speed mode with the SSBY bit in SBYCR = 1, the LSON bit in LPWRCR = 1, the DTON bit = 1, and the PSS bit in TCSR (WDT1) = 1, to make a direct transition to subactive mode. Direct Transition from Subactive Mode to High-Speed Mode: Execute the SLEEP instruction in subactive mode with the SSBY bit in SBYCR = 1, the LSON bit in LPWRCR = 0, the DTON bit = 1, and the PSS bit in TCSR (WDT_1) = 1, to make a direct transition to high-speed mode after the time set in the STS2 to STS0 bits in SBYCR has elapsed. Rev. 1.00 Jan. 29, 2008 Page 593 of 666 REJ09B0427-0100 Section 21 Power-Down Modes 21.11 Clock Output Control The output of the clock can be controlled by means of the PSTOP bit in SCKCR and DDR for the corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle, and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, clock output is disabled and input port mode is set. Table 21.4 shows the state of the pin in each processing state. PLL circuit of this LSI is effective to eliminate the EMI* with lowering the resonator frequency or disabling the clock output. This should be well taken into consideration for the users' system board design Note * EMI (Electromagnetic Interference) Pin State in Each Processing State 0 - High impedance High impedance Fixed high 1 0 1 Table 21.4 DDR PSTOP Hardware Standby Mode Software Standby Mode, Watch Mode, Direct Transitions Sleep Mode, Subsleep Mode High-Speed Mode, Medium-Speed Mode, Subactive Mode High impedance High impedance High impedance output output sub output Fixed high Fixed high Fixed high Rev. 1.00 Jan. 29, 2008 Page 594 of 666 REJ09B0427-0100 Section 21 Power-Down Modes 21.12 Usage Notes 21.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode and watch mode. When the OPE bit is set to 1, the address bus and bus control signal outputs are also retained. Therefore, when a high level is output, the current consumption is not diminished by the amount of current to support the high level output. 21.12.2 Current Consumption during Oscillation Stabilization Wait Period The current consumption increases during the oscillation stabilization wait period. 21.12.3 DTC Module Stop Setting The MSTPA6 bits cannot be set to 1 depending on the DTC operating status. Module stop mode for the DTC must be specified while the DTC is stopped. For details, see section 8, Data Transfer Controller (DTC). 21.12.4 On-Chip Peripheral Module Interrupts Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source activation source. Interrupts should therefore be disabled before entering module stop mode. 21.12.5 Writing to MSTPCR MSTPCR should only be written to by the CPU. Rev. 1.00 Jan. 29, 2008 Page 595 of 666 REJ09B0427-0100 Section 21 Power-Down Modes 21.12.6 Transition to Subactive Mode 1. When making a transition to subactive mode or watch mode, set the DTC to enter module stop mode (write 1 to the relevant bits in MSTPCR), and then read the relevant bits to confirm that they are set to 1 before mode transition. Do not clear module stop mode (write 0 to the relevant bits in MSTPCR) until a transition from subactive mode to high-speed mode or medium-speed mode has been performed. If a DTC activation source occurs in subactive mode, the DTC will be activated only after module stop mode has been cleared and high-speed mode or medium-speed mode has been entered. 2. The on-chip peripheral modules (DTC and TPU) which halt operation in subactive mode cannot clear an interrupt in subactive mode. Therefore, if a transition is made to subactive mode while an interrupt is requested, the CPU interrupt source cannot be cleared. Disable the interrupts of each on-chip peripheral module before executing a SLEEP instruction to enter subactive mode or watch mode. 3. A 1 is always returned when an attempt is made to read the pin status of I/O ports 1, 4, 9, or F during operation in subactive mode. (In the case of port 1, pins 13 to 10 are readable.) In addition, the ports may be used as output ports (except for ports 4 and 9). The procedure for determining the pin status during operation in subactive mode is as follows. [1] Use ports 3, A, B, C, D, E, H, and J as input ports. [2] Use external interrupt inputs (IRQ0 to IRQ5). (If the level sense setting has been selected for the IRQ pins, an interrupt request is generated by a low-level input.) 4. Operation cannot be guaranteed if a transition is made to the subactive mode, subsleep mode, or watch mode when the SUBSTP bit in LPWRCR is set to 1 (subclock generation prohibited). To prevent problems, it should be confirmed that the SUBSTP bit has been cleared to 0 before transitioning to the subactive mode, subsleep mode, or watch mode. Rev. 1.00 Jan. 29, 2008 Page 596 of 666 REJ09B0427-0100 Section 22 List of Registers Section 22 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. * * * * 2. * * * * 3. Register addresses (address order) Registers are listed in the order of ascending addresses. For 16-bit registers, the addresses of MSB are shown. Registers are classified according to functional modules. The access size is indicated. Register bits Bit configurations of the registers are listed in the same order as the register addresses. Reserved bits are indicated by "" in the bit name columns. Registers for which bit numbers are shown are those operate as counters or hold data. For 16-bit registers, bits in MSB are shown in the upper line and bits in LSB in the lower line. Register states in each operating mode * Register states are listed in the same order as the register addresses. * The register states shown here are for the basic operating modes. If an on-chip module has its own reset state, refer to the section on that on-chip module. Rev. 1.00 Jan. 29, 2008 Page 597 of 666 REJ09B0427-0100 Section 22 List of Registers 22.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Data Number of Bus Access Width States Register Name Number Abbreviation of Bits Address* Module PWM control register_1 PWM output control register_1 PWM polarity register_1 PWM cycle register_1 PWM buffer register_1A PWM buffer register_1C PWM buffer register_1E PWM buffer register_1G PWM control register_2 PWM output control register_2 PWM polarity register_2 PWM cycle register_2 PWM buffer register_2A PWM buffer register_2B PWM buffer register_2C PWM buffer register_2D Port H data direction register Port J data direction register Port H data register Port J data register Port H register Port J register Module stop control register D PWCR_1 PWOCR_1 PWPR_1 PWCYR_1 8 8 8 16 H'FC00 H'FC02 H'FC04 H'FC06 H'FC08 H'FC0A H'FC0C H'FC0E H'FC10 H'FC12 H'FC14 H'FC16 H'FC18 H'FC1A H'FC1C H'FC1E H'FC20 H'FC21 H'FC24 H'FC25 H'FC28 H'FC29 H'FC60 PWM_1 PWM_1 PWM_1 PWM_1 PWM_1 PWM_1 PWM_1 PWM_1 PWM_2 PWM_2 PWM_2 PWM_2 PWM_2 PWM_2 PWM_2 PWM_2 PORT PORT PORT PORT PORT PORT 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PWBFR_1A 16 PWBFR_1C 16 PWBFR_1E 16 PWBFR_1G 16 PWCR_2 PWOCR_2 PWPR_2 PWCYR_2 8 8 8 16 PWBFR_2A 16 PWBFR_2B 16 PWBFR_2C 16 PWBFR_2D 16 PHDDR PJDDR PHDR PJDR PORTH PORTJ MSTPCRD 8 8 8 8 8 8 8 SYSTEM 8 Rev. 1.00 Jan. 29, 2008 Page 598 of 666 REJ09B0427-0100 Section 22 List of Registers Register Name Number Abbreviation of Bits Address* Module Number of Data Access Bus Width States Serial Control Register X DDC Switch Register Standby control register System control register System clock control register Mode control register Module stop control register A Module stop control register B Module stop control register C Pin function control register Low power control register Break address register A Break address register B Break control register A Break control register B IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC enable register F DTC enable register G DTC vector register PPG output control register PPG output mode register Next data enable register H SCRX DDCSWR SBYCR SYSCR SCKCR MDCR MSTPCRA MSTPCRB MSTPCRC PFCR LPWRCR BARA BARB BCRA BCRB ISCRH ISCRL IER ISR DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTVECR PCR PMR NDERH 8 8 8 8 8 8 8 8 8 8 8 32 32 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FDB4 H'FDB5 H'FDE4 H'FDE5 H'FDE6 H'FDE7 H'FDE8 H'FDE9 H'FDEA H'FDEB H'FDEC H'FE00 H'FE04 H'FE08 H'FE09 H'FE12 H'FE13 H'FE14 H'FE15 H'FE16 H'FE17 H'FE18 H'FE19 H'FE1A H'FE1B H'FE1C H'FE1F H'FE26 H'FE27 H'FE28 IIC IIC 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 BSC 8 SYSTEM 8 PBC PBC PBC PBC INT INT INT INT DTC DTC DTC DTC DTC DTC DTC DTC PPG PPG PPG 32 32 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Rev. 1.00 Jan. 29, 2008 Page 599 of 666 REJ09B0427-0100 Section 22 List of Registers Register Name Number Abbreviation of Bits Address* Module Number of Data Access Bus Width States Next data enable register L Output data register H Output data register L Next data register H Next data register L Next data register H Next data register L Port 1 data direction register Port 3 data direction register Port A data direction register Port B data direction register Port C data direction register Port D data direction register Port E data direction register Port F data direction register Port A pull-up MOS control register Port B pull-up MOS control register Port C pull-up MOS control register Port D pull-up MOS control register Port E pull-up MOS control register NDERL PODRH PODRL NDRH NDRL NDRH NDRL P1DDR P3DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PAPCR PBPCR PCPCR PDPCR PEPCR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE29 H'FE2A H'FE2B H'FE2C H'FE2D H'FE2E H'FE2F H'FE30 H'FE32 H'FE39 H'FE3A H'FE3B H'FE3C H'FE3D H'FE3E H'FE40 H'FE41 H'FE42 H'FE43 H'FE44 H'FE46 H'FE47 H'FE48 H'FE49 H'FE80 H'FE81 H'FE82 PPG PPG PPG PPG PPG PPG PPG PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT TPU_3 TPU_3 TPU_3 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Port 3 open-drain control register P3ODR Port A open-drain control register PAODR Port B open-drain control register PBODR Port C open-drain control register PCODR Timer control register_3 Timer mode register_3 Timer I/O control register H_3 TCR_3 TMDR_3 TIORH_3 Rev. 1.00 Jan. 29, 2008 Page 600 of 666 REJ09B0427-0100 Section 22 List of Registers Register Name Number Abbreviation of Bits Address* Module Number of Data Access Bus Width States Timer I/O control register L_3 Timer interrupt enable register_3 Timer status register_3 Timer counter H_3 Timer counter L_3 Timer general register AH_3 Timer general register AL_3 Timer general register BH_3 Timer general register BL_3 Timer general register CH_3 Timer general register CL_3 Timer general register DH_3 Timer general register DL_3 Timer control register_4 Timer mode register_4 Timer I/O control register _4 Timer interrupt enable register_4 Timer status register_4 Timer counter H_4 Timer counter L_4 Timer general register AH_4 Timer general register AL_4 Timer general register BH_4 Timer general register BL_4 Timer control register_5 Timer mode register_5 Timer I/O control register _5 Timer interrupt enable register_5 Timer status register_5 Timer counter H_5 TIORL_3 TIER_3 TSR_3 TCNTH_3 TCNTL_3 TGRAH_3 TGRAL_3 TGRBH_3 TGRBL_3 TGRCH_3 TGRCL_3 TGRDH_3 TGRDL_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNTH_4 TCNTL_4 TGRAH_4 TGRAL_4 TGRBH_4 TGRBL_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNTH_5 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FE83 H'FE84 H'FE85 H'FE86 H'FE87 H'FE88 H'FE89 H'FE8A H'FE8B H'FE8C H'FE8D H'FE8E H'FE8F H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE97 H'FE98 H'FE99 H'FE9A H'FE9B H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Jan. 29, 2008 Page 601 of 666 REJ09B0427-0100 Section 22 List of Registers Register Name Number Abbreviation of Bits Address* Module Number of Data Access Bus Width States Timer counter L_5 Timer general register AH_5 Timer general register AL_5 Timer general register BH_5 Timer general register BL_5 Timer start register Timer synchro register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register J Interrupt priority register K Interrupt priority register L Interrupt priority register M Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L RAM emulation register Port 1 data register Port 3 data register TCNTL_5 TGRAH_5 TGRAL_5 TGRBH_5 TGRBL_5 TSTR TSYR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRL IPRM ABWCR ASTCR WCRH WCRL BCRH BCRL RAMER P1DR P3DR 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FEA7 H'FEA8 H'FEA9 H'FEAA H'FEAB H'FEB0 H'FEB1 H'FEC0 H'FEC1 H'FEC2 H'FEC3 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC9 H'FECA H'FECB H'FECC H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FEDB H'FF00 H'FF02 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU common TPU common INT INT INT INT INT INT INT INT INT INT INT INT BSC BSC BSC BSC BSC BSC 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 FLASH 8 (F-ZTAT) PORT PORT 8 8 Rev. 1.00 Jan. 29, 2008 Page 602 of 666 REJ09B0427-0100 Section 22 List of Registers Register Name Number Abbreviation of Bits Address* Module Number of Data Access Bus Width States Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter H_0 Timer counter L_0 Timer general register AH_0 Timer general register AL_0 Timer general register BH_0 Timer general register BL_0 Timer general register CH_0 Timer general register CL_0 Timer general register DH_0 Timer general register DL_0 Timer control register_1 Timer mode register_1 Timer I/O control register _1 Timer interrupt enable register_1 Timer status register_1 Timer counter H_1 Timer counter L_1 PADR PBDR PCDR PDDR PEDR PFDR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNTH_0 TCNTL_0 TGRAH_0 TGRAL_0 TGRBH_0 TGRBL_0 TGRCH_0 TGRCL_0 TGRDH_0 TGRDL_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNTH_1 TCNTL_1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF09 H'FF0A H'FF0B H'FF0C H'FF0D H'FF0E H'FF10 H'FF11 H'FF12 H'FF13 H'FF14 H'FF15 H'FF16 H'FF17 H'FF18 H'FF19 H'FF1A H'FF1B H'FF1C H'FF1D H'FF1E H'FF1F H'FF20 H'FF21 H'FF22 H'FF24 H'FF25 H'FF26 H'FF27 PORT PORT PORT PORT PORT PORT TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Jan. 29, 2008 Page 603 of 666 REJ09B0427-0100 Section 22 List of Registers Register Name Number Abbreviation of Bits Address* Module Number of Data Access Bus Width States Timer general register AH_1 Timer general register AL_1 Timer general register BH_1 Timer general register BL_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter H_2 Timer counter L_2 Timer general register AH_2 Timer general register AL_2 Timer general register BH_2 Timer general register BL_2 Timer control/status register_0 Timer counter_0 Reset control/status register Serial mode register_0 I C Bus Control Register Bit rate register_0 I C Bus Status Register Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Smart card mode register_0 I C Bus Data Register Serial mode register_1 I C Bus Control Register 2 2 2 2 TGRAH_1 TGRAL_1 TGRBH_1 TGRBL_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNTH_2 TCNTL_2 TGRAH_2 TGRAL_2 TGRBH_2 TGRBL_2 TCSR_0 TCNT_0 RSTCSR SMR_0 ICCR_0 BRR_0 ICSR0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ICDR_0 SMR_1 ICCR_1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF28 H'FF29 H'FF2A H'FF2B H'FF30 H'FF31 H'FF32 H'FF34 H'FF35 H'FF36 H'FF37 H'FF38 H'FF39 H'FF3A H'FF3B H'FF74 H'FF75 H'FF77 H'FF78 H'FF78 H'FF79 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF7E H'FF80 H'FF80 TPU_1 TPU_1 TPU_1 TPU_1 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 WDT_0 WDT_0 WDT_0 SCI_0 IIC_0 SCI_0 IIC_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 IIC_0 SCI_1 IIC_0 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Rev. 1.00 Jan. 29, 2008 Page 604 of 666 REJ09B0427-0100 Section 22 List of Registers Register Name Number Abbreviation of Bits Address* Module Number of Data Access Bus Width States Bit rate register_1 I C Bus Status Register Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Smart card mode register_2 A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Timer control/status register_1 Timer counter_1 D/A Data Register 0 D/A Data Register 1 D/A Control Register Flash memory control register 1 2 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 DADR0 DADR1 DACR FLMCR1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FF81 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FFA2 H'FFA3 H'FFA4 H'FFA5 H'FFA6 H'FFA8 SCI_1 IIC_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 A/D A/D A/D A/D A/D A/D A/D A/D A/D A/D WDT_1 WDT_1 D/A D/A D/A 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 FLASH 8 (F-ZTAT) Rev. 1.00 Jan. 29, 2008 Page 605 of 666 REJ09B0427-0100 Section 22 List of Registers Register Name Number Abbreviation of Bits Address* Module Number of Data Access Bus Width States Flash memory control register 2 Erase block register 1 Erase block register 2 Flash memory power control register Port 1 register Port 2 register Port 3 register Port 4 register Port 5 register Port 9 register Port A register Port B register Port C register Port D register Port F register Note: * FLMCR2 EBR1 EBR2 FLPWCR PORT1 PORT2 PORT3 PORT4 PORT5 PORT9 PORTA PORTB PORTC PORTD PORTF 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBE FLASH 8 (F-ZTAT) FLASH 8 (F-ZTAT) FLASH 8 (F-ZTAT) FLASH 8 (F-ZTAT) PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT 8 8 8 8 8 8 8 8 8 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 The lower 16 bits are indicated. Rev. 1.00 Jan. 29, 2008 Page 606 of 666 REJ09B0427-0100 Section 22 List of Registers 22.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit registers are shown as 2 lines, respectively. Register Abbreviation Bit 7 PWCR_1 PWOCR_1 PWPR_1 PWCYR_1 OE1H OPS1H Bit7 PWBFR_1A DT7 PWBFR_1B DT7 PWBFR_1C DT7 PWBFR_1D DT7 PWCR_2 PWOCR_2 PWPR_2 PWCYR_2 OE2H OPS2H Bit7 PWBFR_2A DT7 PWBFR_2B DT7 PWBFR_2C DT7 PWBFR_2D DT7 Bit 6 OE1G OPS1G Bit6 DT6 DT6 DT6 DT6 OE2G OPS2G Bit6 DT6 DT6 DT6 DT6 Bit 5 IE OE1F OPS1F Bit5 DT5 DT5 DT5 DT5 IE OE2F OPS2F Bit5 DT5 DT5 DT5 DT5 Bit 4 CMF OE1E OPS1E Bit4 OTS DT4 OTS DT4 OTS DT4 OTS DT4 CMF OE2E OPS2E Bit4 TDS DT4 TDS DT4 TDS DT4 TDS DT4 Bit 3 CST OE1D OPS1D Bit3 DT3 DT3 DT3 DT3 CST OE2D OPS2D Bit3 DT3 DT3 DT3 DT3 Bit 2 CKS2 OE1C OPS1C Bit2 DT2 DT2 DT2 DT2 CKS2 OE2C OPS2C Bit2 DT2 DT2 DT2 DT2 Bit 1 CKS1 OE1B OPS1B Bit9 Bit1 DT9 DT1 DT9 DT1 DT9 DT1 DT9 DT1 CKS1 OE2B OPS2B Bit9 Bit1 DT9 DT1 DT9 DT1 DT9 DT1 DT9 DT1 Bit 0 CKS0 OE1A OPS1A Bit8 Bit0 DT8 DT0 DT8 DT0 DT8 DT0 DT8 DT0 CKS0 OE2A OPS2A Bit8 Bit0 DT8 DT0 DT8 DT0 DT8 DT0 DT8 DT0 PWM_2 Module PWM_1 Rev. 1.00 Jan. 29, 2008 Page 607 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation Bit 7 PHDDR PJDDR PHDR PJDR PORTH PORTJ MSTPCRD SCRX DOCSWR SBYCR SYSCR SCKCR MDCR MSTPCRA MSTPCRB MSTPCRC PFCR LPWRCR BARA PH7DDR PJ7DDR PH7DR PJ7DR PH7 PJ7 MSTPD7 SWE SSBY MACS PSTOP MSTPA7 MSTPB7 MSTPC7 DTON BAA23 BAA15 BAA7 BARB BAB23 BAB15 BAB7 BCRA BCRB CMFA CMFB Bit 6 PH6DDR PJ6DDR PH6DR PJ6DR PH6 PJ6 MSTPD6 IICX1 SW STS2 MSTPA6 MSTPB6 MSTPC6 LSON BAA22 BAA14 BAA6 BAB22 BAB14 BAB6 CDA CDB Bit 5 PH5DDR PJ5DDR PH5DR PJ5DR PH5 PJ5 MSTPD5 IICX0 IE STS1 INTM1 MSTPA5 MSTPB5 MSTPC5 NESEL BAA21 BAA13 BAA5 BAB21 BAB13 BAB5 BAMRA2 BAMRB2 Bit 4 PH4DDR PJ4DDR PH4DR PJ4DR PH4 PJ4 MSTPD4 IICE IF STS0 INTM0 MSTPA4 MSTPB4 MSTPC4 SUBSTP BAA20 BAA12 BAA4 BAB20 BAB12 BAB4 BAMRA1 BAMRB1 Bit 3 PH3DDR PJ3DDR PH3DR PJ3DR PH3 PJ3 MSTPD3 CLR3 OPE NMIEG STCS MSTPA3 MSTPB3 MSTPC3 AE3 RFCUT BAA19 BAA11 BAA3 BAB19 BAB11 BAB3 BAMRA0 BAMRB0 Bit 2 PH2DDR PJ2DDR PH2DR PJ2DR PH2 PJ2 MSTPD2 CLR2 SCK2 MDS2 MSTPA2 MSTPB2 MSTPC2 AE2 BAA18 BAA10 BAA2 BAB18 BAB10 BAB2 CSELA1 CSELB1 Bit 1 PH1DDR PJ1DDR PH1DR PJ1DR PH1 PJ1 MSTPD1 CLR1 SCK1 MDS1 MSTPA1 MSTPB1 MSTPC1 AE1 STC1 BAA17 BAA9 BAA1 BAB17 BAB9 BAB1 CSELA0 CSELB0 Bit 0 PH0DDR PJ0DDR PH0DR PJ0DR PH0 PJ0 MSTPD0 CLR0 RAME SCK0 MDS0 MSTPA0 MSTPB0 MSTPC0 AE0 STC0 BAA16 BAA8 BAA0 BAB16 BAB8 BAB0 BIEA BIEB BSC SYSTEM PBC SYSTEM SYSTEM IIC Module PORT Rev. 1.00 Jan. 29, 2008 Page 608 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation Bit 7 ISCRH ISCRL IER ISR DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTVECR PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL P1DDR P3DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PAPCR IRQ3SCB DTCEA7 DTCEB7 DTCEC7 DTCED7 DTCEE7 DTCEF7 DTCEG7 SWDTE G3CMS1 G3INV NDER15 NDER7 POD15 POD7 NDR15 NDR7 P17DDR PB7DDR PC7DDR PD7DDR PE7DDR PF7DDR Bit 6 IRQ3SCA DTCEA6 DTCEB6 DTCEC6 DTCED6 DTCEE6 DTCEF6 DTCEG6 DTVEC6 G3CMS0 G2INV NDER14 NDER6 POD14 POD6 NDR14 NDR6 P16DDR PB6DDR PC6DDR PD6DDR PE6DDR PF6DDR Bit 5 IRQ2SCB IRQ5E IRQ5F DTCEA5 DTCEB5 DTCEC5 DTCED5 DTCEE5 DTCEF5 DTCEG5 DTVEC5 G2CMS1 G1INV NDER13 NDER5 POD13 POD5 NDR13 NDR5 P15DDR P35DDR PB5DDR PC5DDR PD5DDR PE5DDR PF5DDR Bit 4 IRQ2SCA IRQ4E IRQ4F DTCEA4 DTCEB4 DTCEC4 DTCED4 DTCEE4 DTCEF4 DTCEG4 DTVEC4 G2CMS0 G0INV NDER12 NDER4 POD12 POD4 NDR12 NDR4 P14DDR P34DDR PB4DDR PC4DDR PD4DDR PE4DDR PF4DDR Bit 3 IRQ5SCB IRQ1SCB IRQ3E IRQ3F DTCEA3 DTCEB3 DTCEC3 DTCED3 DTCEE3 DTCEF3 DTCEG3 DTVEC3 G1CMS1 G3NOV NDER11 NDER3 POD11 POD3 NDR11 NDR3 P13DDR P33DDR PA3DDR PB3DDR PC3DDR PD3DDR PE3DDR PF3DDR PA3PCR Bit 2 IRQ5SCA IRQ1SCA IRQ2E IRQ2F DTCEA2 DTCEB2 DTCEC2 DTCED2 DTCEE2 DTCEF2 DTCEG2 DTVEC2 G1CMS0 G2NOV NDER10 NDER2 POD10 POD2 NDR10 NDR2 P12DDR P32DDR PA2DDR PB2DDR PC2DDR PD2DDR PE2DDR PA2PCR Bit 1 IRQ4SCB IRQ0SCB IRQ1E IRQ1F DTCEA1 DTCEB1 DTCEC1 DTCED1 DTCEE1 DTCEF1 DTCEG1 DTVEC1 G0CMS1 G1NOV NDER9 NDER1 POD9 POD1 NDR9 NDR1 P11DDR P31DDR PA1DDR PB1DDR PC1DDR PD1DDR PE1DDR PA1PCR Bit 0 IRQ4SCA IRQ0SCA IRQ0E IRQ0F DTCEA0 DTCEB0 DTCEC0 DTCED0 DTCEE0 DTCEF0 DTCEG0 DTVEC0 G0CMS0 G0NOV NDER8 NDER0 POD8 POD0 NDR8 NDR0 P10DDR P30DDR PA0DDR PB0DDR PC0DDR PD0DDR PE0DDR PF0DDR PA0PCR PORT PPG DTC Module INT Rev. 1.00 Jan. 29, 2008 Page 609 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation Bit 7 PBPCR PCPCR PDPCR PEPCR P3ODR PAODR PBODR PCODR TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNTH_3 TCNTL_3 TGRAH_3 TGRAL_3 TGRBH_3 TGRBL_3 TGRCH_3 TGRCL_3 TGRDH_3 TGRDL_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNTH_4 TCNTL_4 PB7PCR PC7PCR PD7PCR PE7PCR PB7ODR PC7ODR CCLR2 IOB3 IOD3 TTGE Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 IOB3 TTGE TCFD Bit15 Bit7 Bit 6 PB6PCR PC6PCR PD6PCR PE6PCR PB6ODR PC6ODR CCLR1 IOB2 IOD2 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 CCLR1 IOB2 Bit14 Bit6 Bit 5 PB5PCR PC5PCR PD5PCR PE5PCR P35ODR PB5ODR PC5ODR CCLR0 BFB IOB1 IOD1 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CCLR0 IOB1 TCIEU TCFU Bit13 Bit5 Bit 4 PB4PCR PC4PCR PD4PCR PE4PCR P34ODR PB4ODR PC4ODR CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CKEG1 IOB0 TCIEV TCFV Bit12 Bit4 Bit 3 PB3PCR PC3PCR PD3PCR PE3PCR P33ODR PA3ODR PB3ODR PC3ODR CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CKEG0 MD3 IOA3 Bit11 Bit3 Bit 2 PB2PCR PC2PCR PD2PCR PE2PCR P32ODR PA2ODR PB2ODR PC2ODR TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 TPSC2 MD2 IOA2 Bit10 Bit2 Bit 1 PB1PCR PC1PCR PD1PCR PE1PCR P31ODR PA1ODR PB1ODR PC1ODR TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit 0 PB0PCR PC0PCR PD0PCR PE0PCR P30ODR PA0ODR PB0ODR PC0ODR TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 TPU_4 TPU_3 Module PORT Rev. 1.00 Jan. 29, 2008 Page 610 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation Bit 7 TGRAH_4 TGRAL_4 TGRBH_4 TGRBL_4 TCR_5 TCNTH_5 TCNTL_5 TGRAH_5 TGRAL_5 TGRBH_5 TGRBL_5 TSTR TSYR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRL IPRM ABWCR ASTCR WCRH WCRL BCRH BCRL Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 ABW7 AST7 W71 W31 ICIS1 Bit 6 Bit14 Bit6 Bit14 Bit6 CCLR1 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 ABW6 AST6 W70 W30 ICIS0 Bit 5 Bit13 Bit5 Bit13 Bit5 CCLR0 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CST5 SYNC5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 ABW5 AST5 W61 W21 BRSTRM Bit 4 Bit12 Bit4 Bit12 Bit4 CKEG1 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CST4 SYNC4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 ABW4 AST4 W60 W20 BRSTS1 Bit 3 Bit11 Bit3 Bit11 Bit3 CKEG0 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CST3 SYNC3 ABW3 AST3 W51 W11 BRSTS0 Bit 2 Bit10 Bit2 Bit10 Bit2 TPSC2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 CST2 SYNC2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 ABW2 AST2 W50 W10 Bit 1 Bit9 Bit1 Bit9 Bit1 TPSC1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 CST1 SYNC1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 ABW1 AST1 W41 W01 WDBE Bit 0 Bit8 Bit0 Bit8 Bit0 TPSC0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 CST0 SYNC0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 ABW0 AST0 W40 W00 BSC TPU common INT TPU_5 Module TPU_4 Rev. 1.00 Jan. 29, 2008 Page 611 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation Bit 7 RAMER Bit 6 Bit 5 Bit 4 Bit 3 RAMS Bit 2 RAM2 Bit 1 RAM1 Bit 0 RAM0 Module FLASH (F-ZTAT) P1DR P3DR PADR PBDR PCDR PDDR PEDR PFDR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNTH_0 TCNTL_0 TGRAH_0 TGRAL_0 TGRBH_0 TGRBL_0 TGRCH_0 TGRCL_0 TGRDH_0 TGRDL_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 P17DR PB7DR PC7DR PD7DR PE7DR PF7DR CCLR2 IOB3 IOD3 TTGE Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 IOB3 TTGE TCFD P16DR PB6DR PC6DR PD6DR PE6DR PF6DR CCLR1 IOB2 IOD2 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 CCLR1 IOB2 P15DR P35DR PB5DR PC5DR PD5DR PE5DR PF5DR CCLR0 BFB IOB1 IOD1 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CCLR0 IOB1 TCIEU TCFU P14DR P34DR PB4DR PC4DR PD4DR PE4DR PF4DR CKEG1 BFA IOB0 IOD0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CKEG1 IOB0 TCIEV TCFV P13DR P33DR PA3DR PB3DR PC3DR PD3DR PE3DR PF3DR CKEG0 MD3 IOA3 IOC3 TGIED TGFD Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CKEG0 MD3 IOA3 P12DR P32DR PA2DR PB2DR PC2DR PD2DR PE2DR TPSC2 MD2 IOA2 IOC2 TGIEC TGFC Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 TPSC2 MD2 IOA2 P11DR P31DR PA1DR PB1DR PC1DR PD1DR PE1DR TPSC1 MD1 IOA1 IOC1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 TPSC1 MD1 IOA1 TGIEB TGFB P10DR P30DR PA0DR PB0DR PC0DR PD0DR PE0DR PF0DR TPSC0 MD0 IOA0 IOC0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 TPSC0 MD0 IOA0 TGIEA TGFA TPU_1 TPU_0 PORT Rev. 1.00 Jan. 29, 2008 Page 612 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation Bit 7 TCNTH_1 TCNTL_1 TGRAH_1 TGRAL_1 TGRBH_1 TGRBL_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNTH_2 TCNTL_2 TGRAH_2 TGRAL_2 TGRBH_2 TGRBL_2 TCSR_0 TCNT_0 RSTCSR SMR_0* Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 IOB3 TTGE TCFD Bit15 Bit7 Bit15 Bit7 Bit15 Bit7 OVF Bit7 WOVF C/A (GM) ICCR_0 BRR_0 ICSR_0 SCR_0 TDR_0 SSR_0* ICE Bit7 ESTP TIE Bit7 TDRE (TDRE) RDR_0 SCMR_0 Bit7 Bit 6 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 CCLR1 IOB2 Bit14 Bit6 Bit14 Bit6 Bit14 Bit6 WT/IT Bit6 RSTE CHR (BLK) IEIC Bit6 STOP RIE Bit6 RDRF (RDRF) Bit6 Bit 5 Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 CCLR0 IOB1 TCIEU TCFU Bit13 Bit5 Bit13 Bit5 Bit13 Bit5 TME Bit5 RSTS PE (PE) MST Bit5 IRTR TE Bit5 ORER (ORER) Bit5 Bit 4 Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 CKEG1 IOB0 TCIEV TCFV Bit12 Bit4 Bit12 Bit4 Bit12 Bit4 Bit4 O/E (O/E) TRS Bit4 AASX RE Bit4 FER (ERS) Bit4 Bit 3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 CKEG0 MD3 IOA3 Bit11 Bit3 Bit11 Bit3 Bit11 Bit3 Bit3 STOP (BCP1) ACKE Bit3 AL MPIE Bit3 PER (PER) Bit3 SDIR Bit 2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 TPSC2 MD2 IOA2 Bit10 Bit2 Bit10 Bit2 Bit10 Bit2 CKS2 Bit2 MP (BCP0) BBSY Bit2 AAS TEIE Bit2 TEND (TEND) Bit2 SINV Bit 1 Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 TPSC1 MD1 IOA1 TGIEB TGFB Bit9 Bit1 Bit9 Bit1 Bit9 Bit1 CKS1 Bit1 CKS1 (CKS1) IRIC Bit1 ADZ CKE1 Bit1 MPB (MPB) Bit1 Bit 0 Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 TPSC0 MD0 IOA0 TGIEA TGFA Bit8 Bit0 Bit8 Bit0 Bit8 Bit0 CKS0 Bit0 CKS0 (CKS0) SCP Bit0 ACKB CKE0 Bit0 MPBT (MPBT) Bit0 SMIF IIC_0 SCI_0 IIC_0 SCI_0 SCI_0 WDT_0 TPU_2 Module TPU_1 Rev. 1.00 Jan. 29, 2008 Page 613 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation Bit 7 ICDR_0 SARX_0 ICMR_0 SAR_0 SMR_1* ICDR7 SVAX6 MLS SVA6 C/A (GM) ICCR_1 BRR_1 ICSR_1 SCR_1 TDR_1 SSR_1* ICE Bit7 ESTP TIE Bit7 TDRE (TDRE) RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 SMR_2* Bit7 ICDR7 SVAX6 MLS SVA6 C/A (GM) BRR_2 SCR_2 TDR_2 SSR_2* Bit7 TIE Bit7 TDRE (TDRE) RDR_2 SCMR_2 ADDRAH ADDRAL ADDRBH Bit7 AD9 AD1 AD9 Bit 6 ICDR6 SVAX5 WAIT SVA5 CHR (BLK) IEIC Bit6 STOP RIE Bit6 RDRF (RDRF) Bit6 ICDR6 SVAX5 WAIT SVA5 CHR (BLK) Bit6 RIE Bit6 RDRF (RDRF) Bit6 AD8 AD0 AD8 Bit 5 ICDR5 SVAX4 CKS2 SVA4 PE (PE) MST Bit5 IRTR TE Bit5 ORER (ORER) Bit5 ICDR5 SVAX4 CKS2 SVA4 PE (PE) Bit5 TE Bit5 ORER (ORER) Bit5 AD7 AD7 Bit 4 ICDR4 SVAX3 CKS1 SVA3 O/E (O/E) TRS Bit4 AASX RE Bit4 FER (ERS) Bit4 ICDR4 SVAX3 CKS1 SVA3 O/E (O/E) Bit4 RE Bit4 FER (ERS) Bit4 AD6 AD6 Bit 3 ICDR3 SVAX2 CKS0 SVA2 STOP (BCP1) ACKE Bit3 AL MPIE Bit3 PER (PER) Bit3 SDIR ICDR3 SVAX2 CKS0 SVA2 STOP (BCP1) Bit3 MPIE Bit3 PER (PER) Bit3 SDIR AD5 AD5 Bit 2 ICDR2 SVAX1 BC2 SVA1 MP (BCP0) BBSY Bit2 AAS TEIE Bit2 TEND (TEND) Bit2 SINV ICDR2 SVAX1 BC2 SVA1 MP (BCP0) Bit2 TEIE Bit2 TEND (TEND) Bit2 SINV AD4 AD4 Bit 1 ICDR1 SVAX0 BC1 SVA0 CKS1 (CKS1) IRIC Bit1 ADZ CKE1 Bit1 MPB (MPB) Bit1 ICDR1 SVAX0 BC1 SVA0 CKS1 (CKS1) Bit1 CKE1 Bit1 MPB (MPB) Bit1 AD3 AD3 Bit 0 ICDR0 FSX BC0 FS CKS0 (CKS0) SCP Bit0 ACKB CKE0 Bit0 MPBT (MPBT) Bit0 SMIF ICDR0 FSX BC0 FS CKS0 (CKS0) Bit0 CKE0 Bit0 MPBT (MPBT) Bit0 SMIF AD2 AD2 A/D SCI_2 IIC_1 IIC_1 SCI_1 IIC_1 SCI_1 SCI_1 Module IIC_0 Rev. 1.00 Jan. 29, 2008 Page 614 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation Bit 7 ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 DADR0 DADR1 DACR FLMCR1 FLMCR2 EBR1 EBR2 FLPWCR PORT1 PORT3 PORT4 PORT9 PORTA PORTB PORTC PORTD PORTF AD1 AD9 AD1 AD9 AD1 ADF TRGS1 OVF Bit7 Bit7 Bit7 DAOE1 FWE FLER EB7 PDWND P17 P47 PB7 PC7 PD7 PF7 Bit 6 AD0 AD8 AD0 AD8 AD0 ADIE TRGS0 WT/IT Bit6 Bit6 Bit6 DA0E0 SWE EB6 P16 P46 PB6 PC6 PD6 PF6 Bit 5 AD7 AD7 ADST TME Bit5 Bit5 Bit5 DAE ESU EB5 EB13 P15 P35 P45 PB5 PC5 PD5 PF5 Bit 4 AD6 AD6 SCAN PSS Bit4 Bit4 Bit4 PSU EB4 EB12 P14 P34 P44 PB4 PC4 PD4 PF4 Bit 3 AD5 AD5 CH3 CKS1 RST/NMI Bit3 Bit3 Bit3 EV EB3 EB11 P13 P33 P43 P93 PA3 PB3 PC3 PD3 PF3 Bit 2 AD4 AD4 CH2 CKS0 CKS2 Bit2 Bit2 Bit2 PV EB2 EB10 P12 P32 P42 P92 PA2 PB2 PC2 PD2 Bit 1 AD3 AD3 CH1 CKS1 Bit1 Bit1 Bit1 E EB1 EB9 P11 P31 P41 P91 PA1 PB1 PC1 PD1 Bit 0 AD2 AD2 CH0 CKS0 Bit0 Bit0 Bit0 P EB0 EB8 P10 P30 P40 P90 PA0 PB0 PC0 PD0 PF1 PORT FLASH (F-ZTAT) DA WDT_1 Module A/D Note: * Parts of the bit functions differ in normal mode and the smart card interface mode. The bit function in smart card interface mode is enclosed in parentheses. Rev. 1.00 Jan. 29, 2008 Page 615 of 666 REJ09B0427-0100 Section 22 List of Registers 22.3 Register Abbreviation PWCR_1 PWOCR_1 PWPR_1 PWCYR_1 PWBFR_1A PWBFR_1C PWBFR_1E PWBFR_1G PWCR_2 PWOCR_2 PWPR_2 PWCYR_2 PWBFR_2A PWBFR_2B PWBFR_2C PWBFR_2D PHDDR PJDDR PHDR PJDR PORTH PORTJ MSTPCRD SCRX DDCSWR Register States in Each Operating Mode High Reset speed Medium speed - - - - - - - - - - - - - - - - - - - - - - - - - Module Sleep - - - - - - - - - - - - - - - - - - - - - - - - - Software Hardware Watch Subactive Subsleep Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - - - - - - - Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - - - - - - - Stop Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module PWM_1 Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - - - - - - - - - - - - - - - - - - - - - - - - - PWM_2 PORT SYSTEM IIC Rev. 1.00 Jan. 29, 2008 Page 616 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation SBYCR SYSCR SCKCR MDCR MSTPCRA MSTPCRB MSTPCRC PFCR LPWRCR BARA BARB BCRA BCRB ISCRH ISCRL IER ISR DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCERG DTVECR PCR PMR High Reset speed Medium speed - - - - - - - - - - - - - - - - - - - - - - - - - - - Module Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - Software Hardware Watch - - - - - - - - - - - - - - - - - - - - - - - - - - - Subactive Subsleep Standby - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Stop - - - - - - - - - - - - - - - - - - - - - - - - - - - Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module SYSTEM Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - BSC SYSTEM PBC INT DTC PPG Rev. 1.00 Jan. 29, 2008 Page 617 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL P1DDR P3DDR PADDR PBDDR PCDDR PDDDR PEDDR PFDDR PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR PBODR PCODR TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 High Reset speed Medium speed - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Module Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Software Hardware Watch - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Subactive Subsleep Standby - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Stop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module PPG Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - PORT TPU_3 Rev. 1.00 Jan. 29, 2008 Page 618 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation TSR_3 TCNTH_3 TCNTL_3 TGRAH_3 TGRAL_3 TGRBH_3 TGRBL_3 TGRCH_3 TGRCL_3 TGRDH_3 TGRDL_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNTH_4 TCNTL_4 TGRAH_4 TGRAL_4 TGRBH_4 TGRBL_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNTH_5 TCNTL_5 TGRAH_5 High Reset speed Medium speed - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Module Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Software Hardware Watch - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Subactive Subsleep Standby - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Stop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module TPU_3 Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - TPU_4 TPU_5 Rev. 1.00 Jan. 29, 2008 Page 619 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation TGRAL_5 TGRBH_5 TGRBL_5 TSTR TSYR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRL IPRM ABWCR ASTCR WCRH WCRL BCRH BCRL RAMER High Reset speed Medium speed - - - - - - - - - - - - - - - - - - - - - - - - Module Sleep - - - - - - - - - - - - - - - - - - - - - - - - Software Hardware Watch - - - - - - - - - - - - - - - - - - - - - - - - Subactive Subsleep Standby - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Stop - - - - - - - - - - - - - - - - - - - - - - - - Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module TPU_5 Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - TPU common INT BSC FLASH (F-ZTAT) P1DR P3DR PADR PBDR PCDR Initialized - Initialized - Initialized - Initialized - Initialized - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Initialized Initialized Initialized Initialized Initialized PORT Rev. 1.00 Jan. 29, 2008 Page 620 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation PDDR PEDR PFDR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNTH_0 TCNTL_0 TGRAH_0 TGRAL_0 TGRBH_0 TGRBL_0 TGRCH_0 TGRCL_0 TGRDH_0 TGRDL_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNTH_1 TCNTL_1 TGRAH_1 TGRAL_1 TGRBH_1 TGRBL_1 High Reset speed Medium speed - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Module Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Software Hardware Watch - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Subactive Subsleep Standby - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Stop - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module PORT Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - TPU_0 TPU_1 Rev. 1.00 Jan. 29, 2008 Page 621 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNTH_2 TCNTL_2 TGRAH_2 TGRAL_2 TGRBH_2 TGRBL_2 TCSR_0 TCNT_0 RSTCSR SMR_0 ICCR_0 BRR_0 ICSR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 ICDR_0 SARX_0 ICMR_0 SAR_0 SMR_1 ICCR_1 BRR_1 High Reset speed Medium speed - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Module Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Software Hardware Watch - - - - - - - - - - - - - - - - - - - Subactive Subsleep Standby - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Initialized Initialized Initialized - - - - - - - - - - - - - - - - - - - - - - - - - - - Initialized Initialized Initialized - - - - - - - - Stop - - - - - - - - - - - - - - - - - - - Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - Initialized Initialized Initialized Initialized Initialized Initialized Module TPU_2 Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - - - WDT_0 SCI_0 IIC_0 SCI_0 IIC_0 SCI_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - - - - - - - - - - - - - - - - - - - - - - IIC_0 Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - SCI_1 IIC_1 SCI_1 Rev. 1.00 Jan. 29, 2008 Page 622 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation ICSR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ICDR_1 SARX_1 ICMR_1 SAR_1 SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR TCSR_1 TCNT_1 DADR0 High Reset speed Medium speed - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Module Sleep - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Software Hardware Watch - - Subactive Subsleep Standby - - - - Initialized Initialized Initialized - - - - - - - - Initialized Initialized Initialized - Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - - - Initialized Initialized Initialized - - - - - - - - Initialized Initialized Initialized - Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - Stop - - Standby Initialized Initialized Initialized Initialized Initialized Initialized - Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module IIC_1 SCI_1 Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - - - - - - - - - - - - - - - - - - - - - - IIC_1 Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - SCI_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - - - - - - - A/D WDT_1 D/A Rev. 1.00 Jan. 29, 2008 Page 623 of 666 REJ09B0427-0100 Section 22 List of Registers Register Abbreviation DADR1 DACR FLMCR1 FLMCR2 EBR1 EBR2 FLPWCR PORT1 PORT3 PORT4 PORT9 PORTA PORTB PORTC PORTD PORTF High Reset speed Medium speed - - - - - - - - - - - - - - - - Module Sleep - - - - - - - - - - - - - - - - Software Hardware Watch - - - - - - - - - - - - - - - - Subactive Subsleep Standby - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Stop - - - - - - - - - - - - - - - - Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized - - - - - - - - - Module D/A Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - Initialized - - - - - - - - - - - - - - - - - - - FLASH (F-ZTAT) PORT Note: is not initialized. Rev. 1.00 Jan. 29, 2008 Page 624 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23.1 lists the absolute maximum ratings. Table 23.1 Absolute Maximum Ratings Item Power supply voltage Input voltage (OSC1, OSC2) Input voltage (XTAL, EXTAL) Input voltage (ports 4 and 9) Input voltage (ports H and J) Symbol VCC Vin Vin Vin Vin Value -0.3 to +7.0 -0.3 +4.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to PWMVCC +0.3 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 Storage temperature Tstg -55 to +125 Unit V V V V V V V V V C C C Input voltage (except XTAL, EXTAL, Vin OSC1, OSC2, ports 4, 9, H and J) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Vref AVCC VAN Topr Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded. Rev. 1.00 Jan. 29, 2008 Page 625 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics 23.2 DC Characteristics Table 23.2 lists the DC characteristics. Table 23.3 lists the permissible output currents. Table 23.2 DC Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)*1 *5 Item Schmitt IRQ0 to IRQ5 trigger input voltage Input high voltage RES, STBY, NMI, FWE, MD2 to MD0 EXTAL Ports 1, 3, F Ports A to E Ports H, J Ports 4 and 9 Input low voltage RES, STBY, NMI, FWE, MD2 to MD0 EXTAL Ports 1, 3, F Ports A to E Ports H, J Ports 4, 9 VIL Symbol VT VT - + Min. 1.0 -- Typ. -- -- -- -- Max. -- VCC x 0.7 -- VCC + 0.3 Unit V Test Conditions VT - VT VIH + - 0.4 VCC - 0.7 V VCC x 0.7 2.2 VCC x 0.8 PWMVCC x 0.8 AVCC x 0.7 -0.3 -- -- -- -- -- -- VCC + 0.3 VCC + 0.3 VCC + 0.3 PWMVCC + 0.3 AVCC + 0.3 0.5 V -0.3 -0.3 -0.3 -0.3 -0.3 -- -- -- -- -- 0.8 0.8 VCC x 0.2 PWMVCC x 0.2 AVCC x 0.2 Rev. 1.00 Jan. 29, 2008 Page 626 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics Item Output high voltage Symbol Ports 1, 3, VOH A to F, H,J (excluding P34 and P35) P34, P35 Ports 1, 3, A to F, H, J (excluding P34 and P35) PWM1A to PWM1H, PWM2A to PWM2H Min. VCC - 0.5 Typ. -- Max. -- Unit V Test Conditions IOH = -200 A VCC - 2.5 3.5 -- -- -- -- IOH = -100 A IOH = -1 mA PWMVCC - 0.5 -- -- IOH = -15 mA Output low voltage All output pins except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H VOL -- -- 0.4 V IOL = 1.6 mA -- -- 0.5 V IOL = 15 mA Input leakage current RES STBY, NMI, MD2 to MD0 Ports 4, 9 | Iin | -- -- -- -- -- -- -- 1.0 1.0 1.0 1.0 A Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V Three-state leakage current (off state) Ports 1, 3, A to F, H, J ITSI -- A Vin = 0.5 V to VCC - 0.5 V MOS input Ports A to E pull-up current -IP 50 -- 300 A Vin = 0 V Rev. 1.00 Jan. 29, 2008 Page 627 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics Item Input capacitance RES NMI All input pins except RES and NMI Current dissipation*2 Normal operation Sleep mode All modules stopped Mediumspeed mode (/32) Subactive mode Subsleep mode Watch mode Standby mode Analog power supply current During A/D and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage Symbol Cin Min. -- -- -- -- -- -- Typ. Max. 30 30 15 Unit pF Test Conditions Vin = 0 V f = 1 MHz Ta = 25C ICC*4 -- -- -- -- 75 65 57 49 90 80 -- -- mA f = 20 MHz mA f = 20 MHz (reference value) -- -- -- -- -- AlCC -- 130 80 30 2.0 -- 1.0 220 160 60 5.0 20 2.0 A Using 32.768 kHz crystal resonator A mA Ta 50C 50C < Ta AVCC = 5.0 V -- AlCC -- 0.1 4.0 5.0 5.0 A mA Vref = 5.0 V -- VRAM 2.0 0.1 -- 5.0 -- A V Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref , and AVSS pins open. Apply a voltage between 4.5 V and 5.5 V to the AVCC and Vref pins by connecting them to VCC, for instance. Set Vref AVCC. 2. Current dissipation values are for VIH (min.) = VCC - 0.5 V, VIL (max.) = 0.5 V with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. The values are for VRAM VCC < 3.0 V, VIH (min.) = VCC x 0.9, and VIL (max.) = 0.3 V. 4. ICC depends on VCC and f as follows: ICC (max.) = 30 (mA) + 0.54 (mA/(MHz x V)) x VCC x f (normal operation) Rev. 1.00 Jan. 29, 2008 Page 628 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics ICC (max.) = 30 (mA) + 0.45 (mA/(MHz x V)) x VCC x f (sleep mode) 5. If the motor-control PWM timer is not used, do not leave the PMWVCC, or PMWVSS pins open. If the motor-control PWM timer is not used, apply a voltage of between 4.5 and 5.5 V to the PWMVCC pin, for instance, by connecting it to VCC. Rev. 1.00 Jan. 29, 2008 Page 629 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics Table 23.3 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) All output pins except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H Symbol IOL Min. -- Typ. -- Max. 10 Unit mA Test condition IOL -- -- -- -- -- -- -- 25 30 40 80 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C Permissible Total of all output pins output low excepting PWM1A to current (total) PWM1H, and PWM2A to PWM2H IOL -- Total of PWM1A to PWM1H, IOL and PWM2A to PWM2H -- -- -- -- -- -- -- 150 180 220 2.0 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C Permissible output high current (per pin) All output pins except PWM1A to PWM1H, PWM2A to PWM2H PWM1A to PWM1H, PWM2A to PWM2H -IOH -- -IOH -- -- -- -- -- -- -- 25 30 40 40 mA mA mA mA Ta = 85C Ta = 25C Ta = -40C Permissible Total of all output pins output high excepting PWM1A to current (total) PWM1H, and PWM2A to PWM2H - IOH -- Total of PWM1A to PWM1H, - IOH and PWM2A to PWM2H -- -- -- -- -- -- 150 180 220 mA mA mA Ta = 85C Ta = 25C Ta = -40C Note: To protect chip reliability, do not exceed the output current values in table 23.3. Rev. 1.00 Jan. 29, 2008 Page 630 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics Table 23.4 Bus Drive Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Applicable Pins: SCL1-0, SDA1-0 Item Schmitt trigger input voltage Symbol VT VT - + Min. 1.0 -- Typ. -- -- -- -- -- -- -- -- -- -- -- Max. -- VCC x 0.7 -- VCC + 0.5 VCC x 0.3 0.7 0.4 0.4 20 1.0 250 Unit V Test Conditions VT - VT Input high voltage Input low voltage Output low voltage VIH VIL VOL + - 0.4 VCC x 0.7 - 0.5 -- -- -- VCC = 4.5 V to 5.5 V V V V IOL = 8 mA, VCC = 4.5 V to 5.5 V IOL = 3 mA, VCC = 4.5 V to 5.5 V IOL = 1.6 mA, VCC = 3.3 V to 5.5 V pF A ns Vin = 0 V, f = 1 MHz, Ta = 25 C Vin = 0.5 V to VCC - 5.5 V Input capacitance Three-state leakage current (off state) SCL, SDA, output fall time Cin ITSI tof -- -- 20 + 0.1Cb Rev. 1.00 Jan. 29, 2008 Page 631 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics 23.3 AC Characteristics Figure 23.1 show, the test conditions for the AC characteristics. 5V RL LSI output pin C RH C = 50 pF: Ports 10 to 13, A to F (In case of expansion bus control signal output pin setting) C = 30 pF: All ports RL = 2.4 k RH = 12 k Input/output timing measurement levels * Low level: 0.8 V * High level: 2.0 V Figure 23.1 Output Load Circuit Rev. 1.00 Jan. 29, 2008 Page 632 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics 23.3.1 Clock Timing Table 23.5 lists the clock timing Table 23.5 Clock Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition 20MHz Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator settling time at reset (crystal) Clock oscillator settling time in software standby (crystal) External clock output stabilization delay time 32-kHz clock oscillation settling time Subclock oscillator frequency Subclock (SUB) cycle time Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT tOSC3 fSUB tSUB Min. 50 15 15 -- -- 20 8 2 -- 32.768 30.5 Max. 250 -- -- 10 10 -- -- -- 2 Unit ns ns ns ns ns ms ms ms s kHz s Figure 23.3 Figure 20.3 Figure 23.3 Test Conditions Figure 23.2 tcyc tCH tCL tCr tCf Figure 23.2 System Clock Timing Rev. 1.00 Jan. 29, 2008 Page 633 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics EXTAL tDEXT VCC tDEXT STBY tOSC1 RES tOSC1 Figure 23.3 Oscillator Settling Timing Rev. 1.00 Jan. 29, 2008 Page 634 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics 23.3.2 Control Signal Timing Table 23.6 lists the control signal timing. Table 23.6 Control Signal Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time IRQ hold time IRQ pulse width (exiting software standby mode) Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 150 10 200 150 10 200 Max. -- -- -- -- -- -- -- -- ns ns ns ns Unit ns tcyc ns Figure 23.5 Test Conditions Figure 23.4 tRESS RES tRESW tRESS Figure 23.4 Reset Input Timing Rev. 1.00 Jan. 29, 2008 Page 635 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics tNMIS NMI tNMIW tNMIH IRQ tIRQW tIRQS IRQ Edge input tIRQS IRQ Level input tIRQH Figure 23.5 Interrupt Input Timing Rev. 1.00 Jan. 29, 2008 Page 636 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics 23.3.3 Bus Timing Table 23.7 lists the bus timing. Table 23.7 Bus Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Address delay time Address setup time Address hold time AS delay time RD delay time 1 RD delay time 2 Read data setup time Read data hold time Read data access time1 Read data access time2 Read data access time3 Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time Symbol tAD tAS tAH tASD tRSD1 tRSD2 tRDS tRDH tACC1 tACC2 tACC3 tACC4 tACC5 tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS tWDH Min. -- 0.5 x tcyc - 20 0.5 x tcyc - 15 -- -- -- 20 0 -- -- -- -- -- -- -- 1.0 x tcyc - 20 1.5 x tcyc - 20 -- 0.5 x tcyc - 20 0.5 x tcyc - 10 Max. 35 -- -- 20 20 20 -- -- 1.0 x tcyc - 48 1.5 x tcyc - 45 2.0 x tcyc - 45 2.5 x tcyc - 45 3.0 x tcyc - 50 20 20 -- -- 30 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 23.6 to Figure 23.10 Rev. 1.00 Jan. 29, 2008 Page 637 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics T1 T2 tAD A23 to A0 tAS AS tRSD2 tASD tASD tAH tRSD1 RD (read) tACC2 tACC3 D15 to D0 (read) tRDS tRDH tWRD2 HWR, LWR (write) tWDD D15 to D0 (write) tWSW1 tWRD2 tWDH Figure 23.6 Basic Bus Timing (Two-State Access) Rev. 1.00 Jan. 29, 2008 Page 638 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics T1 T2 T3 tAD A23 to A0 tAS AS tAH tASD tASD tRSD1 RD (read) tACC4 tRSD2 tACC5 D15 to D0 (read) tRDS tRDH tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2 tWRD2 tWDH Figure 23.7 Basic Bus Timing (Three-State Access) Rev. 1.00 Jan. 29, 2008 Page 639 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics T1 T2 Tw T3 tAD A23 to A0 tAS AS tASD tASD tAH tRSD1 RD (read) D15 to D0 (read) tWRD1 HWR, LWR (write) D15 to D0 (write) tWRD2 tRDS tRSD2 tRDH tWDD tWDS tWDH Figure 23.8 Basic Bus Timing (Three-State Access with One Wait State) Rev. 1.00 Jan. 29, 2008 Page 640 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics T1 T2 or T3 T1 T2 tAD A23 to A0 tAS tAH tASD tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH Figure 23.9 Burst ROM Access Timing (Two-State Access) Rev. 1.00 Jan. 29, 2008 Page 641 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics T1 T2 or T3 T1 tAD A23 to A0 AS tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH Figure 23.10 Burst ROM Access Timing (One-State Access) Rev. 1.00 Jan. 29, 2008 Page 642 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics 23.3.4 Timing of On-Chip Supporting Modules Table 23.8 lists the timing of on-chip supporting modules. Table 23.8 Timing of On-Chip Supporting Modules Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item I/O port Output data delay time Output data delay time 2 Input data setup time Input data hold time PPG TPU Pulse output delay time Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width PWM SCI Single edge Both edges Symbol tPWD tPWD2 tPRS tPRH tPOD tTOCD tTICS tTCKS tTCKWH tTCKWL tMPWMOD Min. -- -- 30 30 -- -- 30 30 1.5 2.5 -- 4 6 tSCKW tSCKr tSCKf tTXD tRXS tRXH tTRGS 0.4 -- -- -- 50 50 50 Max. 50 50 -- -- 50 50 -- -- -- -- 50 -- -- 0.6 1.5 1.5 50 -- -- -- ns Figure 23.19 ns Figure 23.18 tScyc tcyc ns tcyc Figure 23.16 Figure 23.17 ns tcyc Figure 23.15 ns ns Figure 23.13 Figure 23.14 Unit ns Test Conditions Figure 23.11 Figure 23.12 Pulse output delay time Input clock cycle Asynchronous tScyc Synchronous Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous) A/D Trigger input setup time converter Rev. 1.00 Jan. 29, 2008 Page 643 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics T1 tPRS Ports 1, 3, 4, 9 A to F (read) tPRH T2 tPWD Ports 1, 3, A to F (write) Figure 23.11 I/O Port Input/Output Timing (Ports 1, 3, 4, 9, A to F) Bus cycle T1 tPRS Ports H, J (read) tPWD2 Ports H, J (write) tPRH T2 T3 T4 Figure 23.12 I/O Port (Ports H and J) Input/Output Timing Rev. 1.00 Jan. 29, 2008 Page 644 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics tPOD PO15 to PO8 Figure 23.13 PPG Output Timing* tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 23.14 TPU Input/Output Timing tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 23.15 TPU Clock Input Timing Rev. 1.00 Jan. 29, 2008 Page 645 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics tMPWMOD PWM1A to PWM1H, PWM2A to PWM2H Figure 23.16 Motor Control PWM Output Timing tSCKW SCK0 to SCK2 tScyc tSCKr tSCKf Figure 23.17 SCK Clock Input Timing SCK0 to SCK2 tTXD TxD0 to TxD2 (transit data) tRXS RxD0 to RxD2 (receive data) tRXH Figure 23.18 SCI Input/Output Timing (Clock Synchronous Mode) tTRGS ADTRG Figure 23.19 A/D Converter External Trigger Input Timing Rev. 1.00 Jan. 29, 2008 Page 646 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics 23.4 I2C Bus Interface Timing Table 23.9 I2C Bus Interface Timing Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, = 5 MHz to maximum operating frequency, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input rise time SCL, SDA input fall time SCL, SDA input spike pulse elimination time SDA input bus free time Start condition input hold time Retransmission start condition input setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load Symbol tSCL tSCLH tSCLL tSr tSf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Cb Min. 12tcyc 3tcyc 5tcyc -- -- -- 5tcyc 3tcyc 3tcyc 3tcyc 0.5tcyc 0 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 7.5tcyc* 300 1tcyc -- -- -- -- -- -- 400 2 Unit ns ns ns ns ns ns ns ns ns ns ns ns pF Notes Figure 23.20 Note: 17.5tcyc can be set according to the clock selected for use by the I C module. For details, see section 14.5, Usage Notes. Rev. 1.00 Jan. 29, 2008 Page 647 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics VIH SDA0 to SDA1 tBUF tSTAH VIL tSCLH tSTAS tSP tSTOS SCL0 to SCL1 P* S* tSf tSCLL tSCL tSr tSDAH Sr * tSDAS Note: * S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr : Retransmission start condition Figure 23.20 I2C Bus Interface Input/Output Timing Rev. 1.00 Jan. 29, 2008 Page 648 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics 23.5 A/D Conversion Characteristics Table 23.10 lists the A/D conversion characteristics. Table 23.10 A/D Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Min. 10 10 -- -- -- -- -- -- -- Typ. 10 -- -- -- -- -- -- 0.5 -- Max. 10 -- 20 5 3.5 3.5 3.5 -- 4.0 Unit bits s pF k LSB LSB LSB LSB LSB Rev. 1.00 Jan. 29, 2008 Page 649 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics 23.6 D/A Conversion Characteristics Table 23.11 shows the D/A conversion characteristics. Table 23.11 D/A Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition Item Resolution Conversion time Absolute accuracy Min. 8 -- -- -- Typ. 8 -- 1.5 -- Max. 8 10 2.0 1.5 Unit bits s LSB LSB 20-pF capacitive load 2-M resistive load 4-M resistive load Test Conditions Rev. 1.00 Jan. 29, 2008 Page 650 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics 23.7 Flash Memory Characteristics Table 23.12 shows the flash memory characteristics. Table 23.12 Flash Memory Characteristics Conditions: VCC =4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = PWMVSS = PLLVSS, AVSS = 0 V Ta = 0 to +75C (Programming/erasing operating temperature range: regular specification) Item 124 Programming time* * * Symbol Min. tP tE NWEC 1 Typ. 10 100 -- 1 50 30 200 10 Max. 200 1200 100 -- -- 32 202 12 Unit ms/ 128 bytes ms/block Times s s s s s Test Condition -- -- -- 1 50 28 198 8 135 Erase time* * * Reprogramming count Programming Wait time after SWE bit setting* 14 Wait time after P bit setting* * 1 Wait time after PSU bit setting* tsswe tspsu tsp30 tsp200 tsp10 Programming time wait Programming time wait Additionalprogramming time wait Wait time after P bit clear* 1 tcp tcpsu tspv tspvr tcpv tcswe 1 1 5 5 4 2 2 100 -- 1 100 10 20 5 5 4 2 2 100 -- 1 100 10 20 -- -- -- -- -- -- 1000 -- -- 100 -- s s s s s s Times s s ms s Erase time wait 1 Wait time after PSU bit clear* Wait time after PV bit setting* Wait time after H'FF dummy 1 write* Wait time after PV bit clear* 1 1 Wait time after SWE bit clear* 14 Maximum programming count* * N Erase Wait time after SWE bit setting* 15 Wait time after E bit setting* * tsswe tsesu tse tsev 1 Wait time after ESU bit setting* Wait time after EV bit setting* 1 Rev. 1.00 Jan. 29, 2008 Page 651 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics Test Condition Item Erase Wait time after E bit clear* 1 1 Wait time after ESU bit clear* Symbol Min. tce tcesu tsevr tcev tcswe N 10 10 2 4 100 12 Typ. 10 10 2 4 100 -- Max. -- -- -- -- -- 120 Unit s s s s s Times Wait time after H'FF dummy 1 write* Wait time after EV bit clear* 15 Maximum erase count* * 1 1 Wait time after SWE bit clear* Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 128 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time) 3. Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time) 4. To specify the maximum programming time value (tP (max.)) in the 128-byte programming algorithm, set the max. value (1000) for the maximum programming count (N). The wait time after P bit setting should be changed as follows according to the value of the programming counter (n). Programming counter (n) = 1 to 6: tsp30 = 30 s Programming counter (n) = 7 to 1000: tsp200 = 200 s [In additional programming] Programming counter (n)= 1 to 6: tsp10 = 10 s 5. For the maximum erase time (tE (max.)), the following relationship applies between the wait time after E bit setting (tse) and the maximum erase count (N): tE (max.) = Wait time after E bit setting (tse) x maximum erase count (N) To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy the above formula. Examples: When tse = 100 [ms], N = 12 times When tse = 10 [ms], N = 120 times Rev. 1.00 Jan. 29, 2008 Page 652 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics 23.8 Usage Note Although both the F-ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, there may be differences in the actual values of the electrical characteristics, operating margins, noise margins, and so forth, due to differences in the fabrication process, the on-chip ROM, and the layout patterns. Therefore, if a system is evaluated using the F-ZTAT version, a similar evaluation should also be performed using the mask ROM version. Rev. 1.00 Jan. 29, 2008 Page 653 of 666 REJ09B0427-0100 Section 23 Electrical Characteristics Rev. 1.00 Jan. 29, 2008 Page 654 of 666 REJ09B0427-0100 Appendix Appendix A. I/O Port States in Each Operating State MCU Operating Mode 4 and 5 6 Hardware Power-on Standby Reset Mode T T Program Execution State, Software Standby Mode Sleep Mode P10 to P13 T P10 to P13 A20 to A23 Port Name Port 1 [Address output, OPE = 0] [Address output] [Address output, OPE = 1] [Other than the above] Keep [Other than the above] Keep P14 to P17 Keep I/O port P14 to P17 I/O port 7 Port 3 Port 4 Port 9 Port A 4 to 7 4 to 7 4 to 7 4 and 5 6 T T T L T T T T T Keep Keep T T T P10 to P17 I/O port I/O port Input port Input port A19 to A17 [Address output, OPE = 0] [Address output] [Address output, OPE = 1] [Other than the above] Keep [Other than the above] Keep I/O port 7 T T Keep I/O port Rev. 1.00 Jan. 29, 2008 Page 655 of 666 REJ09B0427-0100 Appendix Port Name Port B MCU Operating Mode 4 and 5 6 Hardware Power-on Standby Reset Mode L T T Program Execution State, Software Standby Mode Sleep Mode [Address output, OPE = 0] [Address output] T A15 to A8 [Address output, OPE = 1] [Other than the above] Keep [Other than the above] Keep I/O port 7 Port C 4 and 5 T L T T Keep [OPE = 0] T [OPE = 1] Keep I/O port A7 to A0 6 T T [DDR = 1, OPE = 0] T [DDR = 1, OPE = 1] Keep [DDR = 0] Keep [DDR = 1] A7 to A0 [DDR = 0] Input port 7 Port D 4 to 6 7 Port E 4 to 6 8-bit bus T T T T T T T T T T T Keep T Keep Keep T Keep [DDR = 0] T [DDR = 1] H I/O port Data bus I/O port I/O port Data bus I/O port [DDR = 0] T [DDR = 1] Clock output 16-bit T bus 7 PF7/ 4 to 6 7 T Clock output T Rev. 1.00 Jan. 29, 2008 Page 656 of 666 REJ09B0427-0100 Appendix Port Name PF6/AS MCU Operating Mode 4 to 6 Hardware Power-on Standby Reset Mode H T Program Execution State, Software Standby Mode Sleep Mode [OPE = 0] T [OPE = 1] H AS 7 PF5/RD, PF4/HWR 4 to 6 T H T T Keep [OPE = 0] T [OPE = 1] H I/O port RD, HWR 7 PF3/LWR 4 to 6 T H T T Keep [OPE = 0] T [OPE = 1] H I/O port LWR 7 PF0 Port H Port J 4 to 7 4 to 7 4 to 7 T T T T T T T T Keep Keep Keep Keep I/O port I/O port I/O port I/O port [Legend] H: High level L: Low level T: High impedance Keep: Input port becomes high-impedance, and output port retains state Port: Depends on the port setting (input becomes high-impedance) DDR: Data direction register OPE: Output port enable WAITE: Wait input enable Rev. 1.00 Jan. 29, 2008 Page 657 of 666 REJ09B0427-0100 Appendix B. Product Code Lineup Product Code F-ZTAT version HD64F2607 Mark Code HD64F2607WF20 (Normal spec) Package (Renesas Package Code) 128-pin QFP Product Type H8S/2607 group PRQP0128KB-A HD64F2607WF20W (FP-128B/FP-128BV) (Wide Temperature Range spec) HD64F2607WF20V (Normal spec) HD64F2607WF20WV (Wide Temperature Range spec) Masked ROM version HD6432607 HD6432607W(***)F (Normal spec) HD6432607W(***)FW (Wide Temperature Range spec) HD6432607W(***)FV (Normal spec) HD6432607W(***)FWV (Wide Temperature Range spec) HD6432606 HD6432606W(***)F (Normal spec) HD6432606W(***)FW (Wide Temperature Range spec) HD6432606W(***)FV (Normal spec) HD6432606W(***)FWV (Wide Temperature Range spec) HD6432605 HD6432605W(***)F (Normal spec) HD6432605W(***)FW (Wide Temperature Range spec) HD6432605W(***)FV (Normal spec) HD6432605W(***)FWV (Normal spec) [Legend] (***): ROM code Rev. 1.00 Jan. 29, 2008 Page 658 of 666 REJ09B0427-0100 Appendix C. Package Dimensions The package dimensions that are shown in the Renesas Semiconductor Package Data Book have priority. JEITA Package Code P-QFP128-14x20-0.50 RENESAS Code PRQP0128KB-A Previous Code FP-128B/FP-128BV MASS[Typ.] 1.7g HD *1 D 65 64 102 103 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp *2 HE E b1 c1 39 ZE c 128 1 ZD Index mark 38 Terminal cross section Reference Dimension in Millimeters Symbol F e *3 A1 L L1 y bp x M Detail F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 20 14 2.70 21.8 22.0 22.2 15.8 16.0 16.2 3.15 0.00 0.10 0.25 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.10 0.10 0.75 0.75 0.3 0.5 0.7 1.0 Min A A2 Figure C.1 FP-128B Package Dimensions Rev. 1.00 Jan. 29, 2008 Page 659 of 666 REJ09B0427-0100 c Appendix Rev. 1.00 Jan. 29, 2008 Page 660 of 666 REJ09B0427-0100 Index Numerics 16-bit timer pulse unit (TPU) ................. 229 C Cascaded operation ................................. 280 Chain transfer.................................. 156, 162 Clock pulse generator ............................. 565 Condition field .......................................... 42 Condition-code register (CCR) ................. 26 Conversion time ...................................... 493 CPU operating modes ............................... 18 A A/D converter ......................................... 485 A/D converter activation......................... 295 Absolute address....................................... 44 Activation by software............................ 160 Address map ............................................. 58 Address space ........................................... 22 Addressing modes..................................... 43 ADI ......................................................... 495 Advanced mode ........................................ 20 Arithmetic operations instructions............ 34 Asynchronous mode ............................... 373 D D/A converter ......................................... 503 Data size and data alignment .................. 117 Data transfer controller ........................... 139 Data transfer instructions .......................... 33 Direct transitions..................................... 593 DTC vector table..................................... 148 B Basic bus interface.................................. 117 Basic timing.................................... 120, 129 Bcc...................................................... 31, 39 Bit manipulation instructions.................... 37 Bit rate .................................................... 366 Block data transfer instructions ................ 41 Block transfer mode................................ 154 Boot mode .............................................. 547 Branch instructions ................................... 39 Break....................................................... 416 Break address...................................... 95, 98 Break condition......................................... 98 Buffer operation...................................... 276 Burst ROM interface............................... 129 Bus arbitration ........................................ 136 Bus controller ......................................... 105 E Effective address................................. 43, 46 Effective address extension....................... 42 Emulation................................................ 551 Erase/erase-verify ................................... 556 Erasing units ........................................... 538 Error protection....................................... 558 Exception handling ................................... 61 Extended control register (EXR)............... 25 External trigger ....................................... 495 F Flash memory ......................................... 533 Framing error .......................................... 380 Free-running count operation.................. 269 Rev. 1.00 Jan. 29, 2008 Page 661 of 666 REJ09B0427-0100 G General registers ....................................... 24 N NMI .......................................................... 80 Non-overlapping pulse output................. 329 Normal mode ............................ 18, 152, 161 H Hardware protection ............................... 558 Hardware standby mode ......................... 589 O On-board programming .......................... 547 Operating mode selection ......................... 53 Operation field .......................................... 42 Output trigger.......................................... 323 Overflows ............................................... 344 Overrun error .......................................... 380 I Idle cycle ................................................ 132 Immediate ................................................. 45 Input capture........................................... 272 Instruction set ........................................... 31 Interrupt .................................................... 67 Interrupt control mode .............................. 85 Interrupt controller.................................... 71 Interrupt exception handling vector table ................................ 81 Interrupt mask bit ..................................... 26 Interrupt mask level .................................. 25 Interrupt priority register (IPR) ................ 71 Interval timer mode ................................ 346 P Parity error .............................................. 380 PC break controller ................................... 95 Periodic count operation ......................... 269 Phase counting mode .............................. 287 PLL circuit .............................................. 571 Power-down modes................................. 575 Program counter (PC) ............................... 25 Program/erase protection ........................ 558 Program/program-verify ......................... 554 Program-counter relative .......................... 45 Programmable pulse generator ............... 315 Programmer mode................................... 560 PWM mode............................................. 282 L List of registers ....................................... 597 Logic operations instructions.................... 36 M MAC instruction....................................... 55 Mark state ............................................... 416 Medium-speed mode .............................. 585 Memory indirect ....................................... 45 Module stop mode .................................. 592 Motor control PWM timer (PWM)......... 509 Multiply-accumulate register (MAC) ....... 27 R Register addresses................................... 598 Register bits ............................................ 607 Register direct ........................................... 43 Register field............................................. 42 Register indirect........................................ 43 Register indirect with displacement.......... 44 Register indirect with post-increment ....... 44 Register indirect with pre-decrement........ 44 Rev. 1.00 Jan. 29, 2008 Page 662 of 666 REJ09B0427-0100 Register information ............................... 148 Register states in each operating mode... 616 Registers ABWCR ..................... 108, 602, 611, 620 ADCR ......................... 491, 605, 615, 623 ADCSR....................... 489, 605, 615, 623 ADDR......................... 488, 605, 614, 623 ASTCR ....................... 108, 602, 611, 620 BARA ........................... 96, 599, 608, 617 BARB ........................... 97, 599, 608, 617 BCRA ........................... 97, 599, 608, 617 BCRB ........................... 98, 599, 608, 617 BCRH ......................... 111, 602, 611, 620 BCRL.......................... 112, 602, 611, 620 BRR ............................ 366, 604, 613, 622 CRA.................................................... 144 CRB .................................................... 144 DACR ......................... 505, 605, 615, 624 DADR0....................... 504, 605, 615, 623 DADR1....................... 504, 605, 615, 624 DAR.................................................... 144 DTCER ....................... 145, 599, 609, 617 DTVECR .................... 146, 599, 609, 617 EBR1 .......................... 543, 606, 615, 624 EBR2 .......................... 544, 606, 615, 624 FLMCR1..................... 541, 605, 615, 624 FLMCR2..................... 542, 606, 615, 624 FLPWCR .................... 546, 606, 615, 624 IER................................ 76, 599, 609, 617 IPR................................ 75, 602, 611, 620 ISCR ............................. 77, 599, 609, 617 ISR................................ 79, 599, 609, 617 LPWRCR.................... 582, 599, 608, 617 MDCR .......................... 54, 599, 608, 617 MRA ................................................... 142 MRB ................................................... 143 MSTPCR .................... 583, 599, 608, 617 NDER ......................... 318, 599, 609, 618 NDR............................ 320, 600, 609, 618 P1DDR ....................... 170, 600, 609, 618 P1DR........................... 171, 602, 612, 620 P3DDR........................ 184, 600, 609, 618 P3DR........................... 185, 602, 612, 620 P3ODR........................ 186, 600, 610, 618 PADDR....................... 191, 600, 609, 618 PADR.......................... 192, 603, 612, 620 PAODR....................... 193, 600, 610, 618 PAPCR........................ 193, 600, 609, 618 PBDDR ....................... 197, 600, 609, 618 PBDR .......................... 198, 603, 612, 620 PBODR ....................... 199, 600, 610, 618 PBPCR ........................ 199, 600, 610, 618 PCDDR ....................... 208, 600, 609, 618 PCDR .......................... 209, 603, 612, 620 PCODR ....................... 210, 600, 610, 618 PCPCR ........................ 210, 600, 610, 618 PCR............................. 323, 599, 609, 617 PDDDR....................... 212, 600, 609, 618 PDDR.......................... 213, 603, 612, 621 PDPCR........................ 214, 600, 610, 618 PEDDR ....................... 215, 600, 609, 618 PEDR .......................... 216, 603, 612, 621 PEPCR ........................ 217, 600, 610, 618 PFCR........................... 113, 599, 608, 617 PFDDR........................ 218, 600, 609, 618 PFDR .......................... 219, 603, 612, 621 PHDDR....................... 222, 598, 608, 616 PHDR.......................... 223, 598, 608, 616 PJDDR ........................ 225, 598, 608, 616 PJDR ........................... 226, 598, 608, 616 PMR ............................ 324, 599, 609, 617 PODR.......................... 319, 600, 609, 618 PORT1 ........................ 171, 606, 615, 624 PORT2 ................................................ 606 PORT3 ........................ 185, 606, 615, 624 PORT4 ........................ 189, 606, 615, 624 PORT5 ................................................ 606 PORT9 ........................ 190, 606, 615, 624 PORTA ....................... 192, 606, 615, 624 PORTB........................ 198, 606, 615, 624 Rev. 1.00 Jan. 29, 2008 Page 663 of 666 REJ09B0427-0100 PORTC ........................209, 606, 615, 624 PORTD ........................213, 606, 615, 624 PORTE ............................................... 216 PORTF.........................219, 606, 615, 624 PORTH ........................223, 598, 608, 616 PORTJ .........................226, 598, 608, 616 PWBFR .......................523, 598, 607, 616 PWCNT .............................................. 516 PWCR..........................514, 598, 607, 616 PWCYR.......................517, 598, 607, 616 PWDTR .............................................. 518 PWOCR.......................515, 598, 607, 616 PWPR ..........................516, 598, 607, 616 RAMER.......................545, 602, 612, 620 RDR.............................354, 604, 613, 622 RSR .................................................... 354 RSTCSR ......................343, 604, 613, 622 SAR .................................................... 144 SBYCR........................579, 599, 608, 617 SCKCR........................566, 599, 608, 617 SCMR..........................365, 604, 613, 622 SCR .............................358, 604, 613, 622 SMR.............................355, 604, 613, 622 SSR..............................361, 604, 613, 622 SYSCR ..........................55, 599, 608, 617 TCNT..........................266, 339, 603, 604, .....................................612, 613, 621, 622 TCR .............................237, 603, 612, 621 TCSR ...........................339, 604, 613, 622 TDR .............................355, 604, 613, 622 TGR .............................266, 603, 612, 621 TIER ............................261, 603, 612, 621 TIOR............................244, 603, 612, 621 TMDR .........................242, 603, 612, 621 TSR......................263, 355, 603, 612, 621 TSTR ...........................266, 602, 611, 620 TSYR...........................267, 602, 611, 620 WCR............................109, 602, 611, 620 Repeat mode ........................................... 153 Reset ......................................................... 63 Rev. 1.00 Jan. 29, 2008 Page 664 of 666 REJ09B0427-0100 Reset exception handling .......................... 63 S Scan mode............................................... 492 Serial communication interface (SCI)..... 351 Shift instructions ....................................... 36 Single mode ............................................ 492 Sleep mode.............................................. 586 Software activation ......................... 157, 163 Software protection................................. 558 Software standby mode........................... 587 Stack pointer (SP) ..................................... 24 Stack status ............................................... 69 Subactive mode....................................... 591 Subsleep mode ........................................ 591 SWDTEND............................................. 157 Synchronous operation............................ 274 System control instructions....................... 40 T TCIU_1 ................................................... 294 TCIU_2 ................................................... 294 TCIU_4 ................................................... 294 TCIU_5 ................................................... 294 TCIV_0 ................................................... 294 TCIV_1 ................................................... 294 TCIV_2 ................................................... 294 TCIV_3 ................................................... 294 TCIV_4 ................................................... 294 TCIV_5 ................................................... 294 TGIA_0................................................... 294 TGIA_1................................................... 294 TGIA_2................................................... 294 TGIA_3................................................... 294 TGIA_4................................................... 294 TGIA_5................................................... 294 TGIB_0 ................................................... 294 TGIB_1 ................................................... 294 TGIB_2................................................... 294 TGIB_3................................................... 294 TGIB_4................................................... 294 TGIB_5................................................... 294 TGIC_0................................................... 294 TGIC_3................................................... 294 TGID_0................................................... 294 TGID_3................................................... 294 Toggle output.......................................... 270 Trace bit.................................................... 25 Traces ....................................................... 66 Trap instruction......................................... 68 TRAPA instruction ............................. 45, 68 U User program mode................................. 550 V Valid strobe............................................. 119 Vector number for the software activation interrupt................................................... 146 W Watch mode ............................................ 590 Watchdog timer (WDT) .......................... 337 Waveform output by compare match...... 270 WOVI...................................................... 346 Write data buffer function....................... 135 Rev. 1.00 Jan. 29, 2008 Page 665 of 666 REJ09B0427-0100 Rev. 1.00 Jan. 29, 2008 Page 666 of 666 REJ09B0427-0100 Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2607 Group Publication Date: Rev.1.00, Jan. 29, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.2 H8S/2607 Group Hardware Manual |
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